Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142108	1			T74	80		T75	1		T76	12
values[2]	12513	1			T74	2		T75	1		T502	1
values[3]	5177	1			T75	1		T502	1		T396	1
values[4]	2852	1			T75	1		T502	1		T396	1
values[5]	1945	1			T75	1		T502	1		T396	1
values[6]	1306	1			T75	1		T502	1		T396	1
values[7]	994	1			T75	1		T502	1		T396	1
values[8]	763	1			T75	1		T502	1		T396	1
values[9]	527	1			T75	1		T502	1		T396	1
values[10]	371	1			T75	1		T502	1		T396	1
values[11]	321	1			T75	1		T502	1		T396	1
values[12]	367	1			T75	1		T502	1		T396	1
values[13]	297	1			T75	1		T502	1		T396	1
values[14]	345	1			T75	1		T502	1		T396	1
values[15]	316	1			T75	1		T502	1		T396	1
values[16]	322	1			T75	1		T502	1		T396	1
values[17]	335	1			T75	1		T502	1		T396	1
values[18]	346	1			T75	1		T502	1		T396	1
values[19]	310	1			T75	1		T502	1		T396	1
values[20]	303	1			T75	1		T502	1		T396	1
values[21]	303	1			T75	1		T502	1		T396	1
values[22]	299	1			T75	1		T502	1		T396	1
values[23]	329	1			T75	1		T502	1		T396	1
values[24]	292	1			T75	1		T502	1		T396	1
values[25]	306	1			T75	1		T502	1		T396	1
values[26]	342	1			T75	1		T502	1		T396	1
values[27]	268	1			T75	1		T502	1		T396	1
values[28]	273	1			T75	1		T502	1		T396	1
values[29]	308	1			T75	1		T502	1		T396	1
values[30]	323	1			T75	1		T502	1		T396	1
values[31]	303	1			T75	1		T502	1		T396	1
values[32]	271	1			T75	1		T502	1		T396	1
values[33]	315	1			T75	1		T502	1		T396	1
values[34]	304	1			T75	1		T502	1		T396	1
values[35]	278	1			T75	1		T502	1		T396	1
values[36]	294	1			T75	1		T502	1		T396	1
values[37]	268	1			T75	1		T502	1		T396	1
values[38]	262	1			T75	1		T502	1		T396	1
values[39]	271	1			T75	1		T502	1		T396	1
values[40]	313	1			T75	1		T502	1		T396	1
values[41]	297	1			T75	1		T502	1		T396	1
values[42]	266	1			T75	1		T502	1		T396	1
values[43]	259	1			T75	1		T502	1		T396	1
values[44]	295	1			T75	1		T502	1		T396	1
values[45]	282	1			T75	1		T502	1		T396	1
values[46]	248	1			T75	1		T502	1		T396	1
values[47]	253	1			T75	1		T502	1		T396	1
values[48]	260	1			T75	1		T502	2		T396	1
values[49]	321	1			T75	1		T502	1		T396	1
values[50]	266	1			T75	1		T502	1		T396	1
values[51]	292	1			T75	1		T502	1		T396	1
values[52]	302	1			T75	1		T502	1		T396	1
values[53]	227	1			T75	2		T502	1		T396	1
values[54]	296	1			T75	1		T502	1		T396	1
values[55]	242	1			T75	1		T502	1		T396	1
values[56]	218	1			T75	1		T502	1		T396	1
values[57]	225	1			T75	1		T502	1		T396	1
values[58]	259	1			T75	1		T502	1		T396	1
values[59]	223	1			T75	1		T502	1		T396	1
values[60]	198	1			T75	1		T502	1		T396	1
values[61]	209	1			T75	1		T502	1		T396	1
values[62]	200	1			T75	1		T502	1		T396	1
values[63]	225	1			T75	1		T502	1		T396	1
values[64]	192	1			T75	1		T502	1		T396	1
values[65]	185	1			T75	1		T502	1		T396	1
values[66]	173	1			T75	1		T502	1		T396	1
values[67]	169	1			T75	1		T502	1		T396	1
values[68]	160	1			T75	1		T502	1		T396	1
values[69]	116	1			T75	1		T502	1		T396	1
values[70]	110	1			T75	1		T502	1		T396	1
values[71]	125	1			T75	1		T502	1		T396	1
values[72]	111	1			T75	1		T502	1		T396	1
values[73]	117	1			T75	1		T502	1		T396	1
values[74]	125	1			T75	1		T502	1		T396	1
values[75]	69	1			T75	1		T502	1		T396	1
values[76]	66	1			T75	1		T502	1		T396	1
values[77]	60	1			T75	1		T502	1		T396	1
values[78]	76	1			T75	1		T502	1		T396	1
values[79]	86	1			T75	1		T502	1		T396	1
values[80]	80	1			T75	1		T502	1		T396	1
values[81]	53	1			T75	1		T502	1		T396	1
values[82]	95	1			T75	1		T502	1		T396	1
values[83]	66	1			T75	1		T502	1		T396	1
values[84]	60	1			T75	1		T502	1		T396	1
values[85]	73	1			T75	1		T502	1		T396	1
values[86]	76	1			T75	1		T502	1		T396	1
values[87]	76	1			T75	1		T502	1		T396	1
values[88]	76	1			T75	1		T502	1		T396	1
values[89]	75	1			T75	1		T502	1		T396	1
values[90]	90	1			T75	1		T502	1		T396	1
values[91]	75	1			T75	1		T502	1		T396	1
values[92]	93	1			T75	1		T502	1		T396	1
values[93]	74	1			T75	1		T502	1		T396	1
values[94]	102	1			T75	1		T502	1		T396	1
values[95]	95	1			T75	1		T502	1		T396	2
values[96]	82	1			T75	1		T502	1		T396	1
values[97]	78	1			T75	1		T502	1		T396	1
values[98]	80	1			T75	1		T502	1		T396	1
values[99]	72	1			T75	1		T502	1		T396	1
values[100]	57	1			T75	1		T502	1		T396	1
values[101]	77	1			T75	1		T502	1		T396	1
values[102]	64	1			T75	1		T502	1		T396	1
values[103]	62	1			T75	2		T502	1		T396	1
values[104]	73	1			T75	2		T502	1		T396	1
values[105]	58	1			T75	2		T502	1		T396	1
values[106]	50	1			T75	1		T502	1		T396	1
values[107]	55	1			T75	1		T502	1		T396	1
values[108]	62	1			T75	2		T502	1		T396	1
values[109]	58	1			T75	4		T502	1		T396	1
values[110]	66	1			T75	2		T502	1		T396	1
values[111]	63	1			T75	1		T502	2		T396	1
values[112]	67	1			T75	1		T502	2		T396	1
values[113]	64	1			T75	1		T502	2		T396	1
values[114]	79	1			T75	1		T502	4		T396	2
values[115]	70	1			T75	2		T502	1		T396	3
values[116]	54	1			T75	1		T502	2		T396	2
values[117]	83	1			T75	3		T502	3		T396	1
values[118]	68	1			T75	2		T502	1		T396	2
values[119]	74	1			T75	5		T502	2		T396	1
values[120]	69	1			T75	4		T502	4		T396	1
values[121]	83	1			T75	3		T502	6		T396	1
values[122]	76	1			T75	3		T502	1		T396	2
values[123]	97	1			T75	1		T502	6		T396	1
values[124]	88	1			T75	1		T502	5		T396	1
values[125]	104	1			T75	1		T502	1		T396	1
values[126]	109	1			T75	2		T502	4		T396	2
values[127]	937	1			T75	32		T502	30		T396	25
values[128]	8922	1			T75	295		T502	246		T396	391