Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136358	1			T74	71		T76	10		T78	4
values[2]	9153	1			T74	1		T514	1		T508	3
values[3]	4634	1			T665	1		T405	4		T799	1
values[4]	2500	1			T665	1		T405	3		T799	1
values[5]	1527	1			T665	1		T405	7		T799	1
values[6]	1087	1			T665	1		T405	6		T799	1
values[7]	840	1			T665	1		T405	5		T799	1
values[8]	652	1			T665	1		T405	2		T799	1
values[9]	717	1			T665	1		T405	1		T799	1
values[10]	659	1			T665	1		T405	2		T799	1
values[11]	562	1			T665	1		T405	3		T799	1
values[12]	592	1			T665	1		T405	5		T799	1
values[13]	641	1			T665	1		T405	3		T799	1
values[14]	589	1			T665	1		T405	4		T799	1
values[15]	589	1			T665	1		T405	2		T799	1
values[16]	564	1			T665	1		T405	3		T799	1
values[17]	512	1			T665	1		T405	5		T799	1
values[18]	576	1			T665	1		T405	4		T799	1
values[19]	516	1			T665	1		T405	1		T799	1
values[20]	493	1			T665	1		T405	3		T799	1
values[21]	555	1			T665	1		T405	1		T799	1
values[22]	505	1			T665	1		T405	4		T799	1
values[23]	424	1			T665	1		T405	4		T799	1
values[24]	420	1			T665	1		T405	1		T799	1
values[25]	492	1			T665	1		T405	2		T799	1
values[26]	514	1			T665	1		T405	3		T799	1
values[27]	466	1			T665	1		T405	12		T799	1
values[28]	357	1			T665	1		T405	3		T799	1
values[29]	425	1			T665	1		T405	13		T799	1
values[30]	448	1			T665	1		T405	2		T799	1
values[31]	443	1			T665	1		T405	1		T799	1
values[32]	439	1			T665	1		T405	7		T799	1
values[33]	428	1			T665	1		T405	4		T799	1
values[34]	386	1			T665	1		T405	3		T799	1
values[35]	348	1			T665	1		T405	4		T799	1
values[36]	413	1			T665	1		T405	5		T799	1
values[37]	374	1			T665	1		T405	6		T799	1
values[38]	384	1			T665	1		T405	6		T799	1
values[39]	360	1			T665	1		T405	7		T799	1
values[40]	366	1			T665	1		T405	11		T799	1
values[41]	356	1			T665	1		T405	12		T799	1
values[42]	383	1			T665	1		T405	10		T799	1
values[43]	343	1			T665	1		T405	8		T799	1
values[44]	365	1			T665	1		T405	4		T799	1
values[45]	266	1			T665	1		T405	5		T799	1
values[46]	258	1			T665	1		T405	3		T799	1
values[47]	225	1			T665	1		T405	4		T799	1
values[48]	203	1			T665	1		T405	3		T799	1
values[49]	224	1			T665	1		T405	3		T799	1
values[50]	153	1			T665	1		T405	2		T799	1
values[51]	137	1			T665	1		T405	6		T799	1
values[52]	180	1			T665	1		T405	2		T799	1
values[53]	133	1			T665	1		T405	8		T799	1
values[54]	118	1			T665	1		T405	4		T799	1
values[55]	116	1			T665	1		T405	1		T799	1
values[56]	93	1			T665	1		T405	2		T799	1
values[57]	98	1			T665	1		T405	3		T799	1
values[58]	89	1			T665	1		T405	2		T799	1
values[59]	97	1			T665	1		T405	6		T799	1
values[60]	109	1			T665	1		T405	7		T799	1
values[61]	102	1			T665	1		T405	4		T799	1
values[62]	103	1			T665	1		T405	5		T799	1
values[63]	89	1			T665	1		T405	6		T799	1
values[64]	97	1			T665	1		T405	1		T799	1
values[65]	108	1			T665	1		T405	3		T799	1
values[66]	112	1			T665	1		T405	3		T799	1
values[67]	121	1			T665	1		T405	4		T799	1
values[68]	89	1			T665	1		T405	3		T799	1
values[69]	107	1			T665	1		T405	6		T799	1
values[70]	102	1			T665	1		T405	4		T799	1
values[71]	114	1			T665	1		T405	4		T799	1
values[72]	131	1			T665	1		T405	7		T799	1
values[73]	123	1			T665	1		T405	6		T799	1
values[74]	143	1			T665	1		T405	1		T799	1
values[75]	105	1			T665	1		T799	1		T447	2
values[76]	96	1			T665	3		T799	1		T447	1
values[77]	84	1			T665	3		T799	1		T447	3
values[78]	113	1			T665	1		T799	1		T447	2
values[79]	99	1			T665	1		T799	3		T447	4
values[80]	105	1			T665	3		T799	9		T447	1
values[81]	142	1			T665	12		T799	6		T447	4
values[82]	129	1			T665	5		T799	6		T447	16
values[83]	111	1			T665	1		T799	3		T447	4
values[84]	104	1			T665	5		T799	1		T447	2
values[85]	93	1			T665	9		T799	3		T447	2
values[86]	102	1			T665	1		T799	1		T447	6
values[87]	100	1			T665	4		T799	4		T447	5
values[88]	88	1			T665	2		T799	3		T447	1
values[89]	76	1			T665	2		T799	1		T447	2
values[90]	74	1			T665	2		T799	2		T447	1
values[91]	70	1			T665	1		T799	1		T447	1
values[92]	92	1			T665	7		T799	3		T447	5
values[93]	98	1			T665	7		T799	2		T447	4
values[94]	81	1			T665	2		T799	5		T447	5
values[95]	70	1			T665	1		T799	2		T447	3
values[96]	86	1			T665	1		T799	2		T447	5
values[97]	96	1			T665	4		T799	2		T447	2
values[98]	82	1			T665	2		T799	4		T447	1
values[99]	66	1			T665	2		T799	2		T815	9
values[100]	72	1			T665	1		T799	3		T815	3
values[101]	56	1			T665	3		T799	1		T815	3
values[102]	58	1			T665	3		T799	3		T815	3
values[103]	66	1			T665	4		T799	5		T815	4
values[104]	52	1			T665	1		T799	3		T815	2
values[105]	45	1			T665	2		T799	2		T815	1
values[106]	37	1			T665	1		T799	1		T815	1
values[107]	48	1			T665	7		T799	1		T815	1
values[108]	49	1			T665	2		T799	1		T815	3
values[109]	43	1			T665	1		T799	7		T815	4
values[110]	46	1			T665	2		T799	1		T815	5
values[111]	50	1			T665	2		T799	1		T815	1
values[112]	41	1			T665	5		T799	1		T815	1
values[113]	53	1			T665	3		T799	1		T815	4
values[114]	56	1			T665	1		T799	1		T815	1
values[115]	45	1			T665	2		T799	2		T815	2
values[116]	56	1			T665	1		T799	1		T815	4
values[117]	30	1			T665	2		T799	1		T815	2
values[118]	37	1			T665	3		T799	1		T815	2
values[119]	43	1			T665	1		T799	1		T815	2
values[120]	54	1			T665	2		T799	1		T815	3
values[121]	53	1			T665	3		T799	2		T815	2
values[122]	41	1			T665	1		T799	2		T815	1
values[123]	57	1			T665	7		T799	1		T815	2
values[124]	55	1			T665	2		T799	3		T815	1
values[125]	46	1			T665	1		T799	1		T815	2
values[126]	95	1			T665	5		T799	7		T815	2
values[127]	1173	1			T665	48		T799	52		T815	59
values[128]	5418	1			T665	226		T799	286		T815	283