Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
923688 |
1 |
|
|
T74 |
439 |
|
T75 |
892 |
|
T76 |
56 |
auto[1] |
521810 |
1 |
|
|
T74 |
239 |
|
T75 |
114 |
|
T76 |
26 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
371795 |
1 |
|
|
T74 |
91 |
|
T75 |
345 |
|
T76 |
3 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
1004112 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
441386 |
1 |
|
|
T74 |
191 |
|
T75 |
341 |
|
T76 |
25 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
118172 |
1 |
|
|
T74 |
31 |
|
T75 |
111 |
|
T78 |
2 |