Unified Coverage Report :: Group Instance : rv_timer

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T75	1		T78	1		T502	1
small_delay	641	1			T74	1		T244	1		T514	1
zero	659	1			T76	1		T79	1		T80	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T78	1		T508	1		T517	1
small_delay	941	1			T74	1		T75	1		T502	1
zero	659	1			T76	1		T79	1		T80	1