Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	443	1			T75	1		T416	1		T525	1
all_values[1]	510	1			T502	1		T80	1		T509	2
all_values[2]	508	1			T244	1		T525	1		T510	8
all_values[3]	473	1			T502	1		T80	1		T244	1
all_values[4]	477	1			T75	2		T80	1		T509	1
all_values[5]	442	1			T244	4		T509	2		T525	4
all_values[6]	480	1			T509	1		T665	1		T405	1
all_values[7]	476	1			T509	1		T405	1		T853	1
all_values[8]	475	1			T502	1		T509	2		T405	1
all_values[9]	480	1			T244	1		T715	1		T405	1
all_values[10]	426	1			T75	2		T509	1		T405	2
all_values[11]	465	1			T405	2		T416	1		T853	1
all_values[12]	498	1			T509	2		T405	4		T805	2
all_values[13]	521	1			T405	2		T805	2		T525	2
all_values[14]	493	1			T502	1		T244	1		T509	1
all_values[15]	491	1			T75	1		T244	1		T805	1
all_values[16]	444	1			T75	2		T502	1		T510	3
all_values[17]	490	1			T502	1		T80	1		T509	1
all_values[18]	535	1			T80	1		T244	1		T509	1
all_values[19]	479	1			T502	1		T405	2		T525	2
all_values[20]	479	1			T75	1		T80	2		T665	1
all_values[21]	444	1			T244	1		T509	4		T405	2
all_values[22]	488	1			T75	1		T244	1		T416	1
all_values[23]	444	1			T502	1		T80	1		T509	1
all_values[24]	470	1			T502	2		T509	1		T715	1
all_values[25]	471	1			T244	1		T405	1		T805	1
all_values[26]	503	1			T75	1		T502	1		T525	1
all_values[27]	467	1			T75	1		T80	1		T244	1
all_values[28]	468	1			T80	2		T509	1		T405	2
all_values[29]	501	1			T244	1		T405	2		T416	1
all_values[30]	456	1			T502	1		T244	1		T509	1
all_values[31]	450	1			T75	1		T244	2		T509	1
all_values[32]	435	1			T75	1		T80	1		T509	1
all_values[33]	472	1			T509	1		T405	2		T525	3
all_values[34]	504	1			T80	1		T509	1		T405	1
all_values[35]	464	1			T75	1		T502	1		T80	1
all_values[36]	444	1			T75	1		T502	1		T80	1
all_values[37]	492	1			T665	2		T405	1		T805	1
all_values[38]	513	1			T80	1		T416	1		T525	2
all_values[39]	477	1			T75	1		T502	1		T509	1
all_values[40]	522	1			T80	2		T509	2		T405	2
all_values[41]	483	1			T75	1		T80	1		T715	1
all_values[42]	459	1			T715	1		T405	2		T853	2
all_values[43]	429	1			T502	1		T509	1		T405	1
all_values[44]	449	1			T80	1		T244	1		T509	1
all_values[45]	463	1			T502	2		T80	1		T405	2
all_values[46]	494	1			T509	1		T405	1		T510	3
all_values[47]	481	1			T80	2		T244	1		T509	1
all_values[48]	452	1			T80	1		T715	1		T405	1
all_values[49]	428	1			T416	1		T525	4		T510	4