Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3592	1			T80	4		T507	4		T509	17
all_values[1]	3542	1			T80	1		T507	1		T509	11
all_values[2]	3508	1			T80	4		T507	1		T509	7
all_values[3]	3585	1			T80	8		T507	1		T509	11
all_values[4]	3606	1			T80	3		T507	2		T509	11
all_values[5]	3550	1			T80	4		T507	2		T509	12
all_values[6]	3546	1			T80	1		T507	1		T509	9
all_values[7]	3531	1			T507	2		T509	15		T405	16
all_values[8]	3504	1			T80	1		T507	3		T509	6
all_values[9]	3696	1			T80	3		T507	3		T509	8
all_values[10]	3638	1			T80	6		T507	2		T509	14
all_values[11]	3554	1			T509	7		T405	16		T853	5
all_values[12]	3581	1			T507	1		T509	12		T405	16
all_values[13]	3579	1			T80	6		T507	2		T509	11
all_values[14]	3551	1			T80	2		T509	10		T405	19
all_values[15]	3683	1			T80	1		T507	1		T509	11
all_values[16]	3467	1			T80	3		T509	8		T405	17
all_values[17]	3550	1			T80	3		T507	4		T509	10
all_values[18]	3590	1			T80	4		T507	4		T509	6
all_values[19]	3529	1			T80	5		T507	4		T509	8
all_values[20]	3506	1			T80	2		T507	1		T509	12
all_values[21]	3627	1			T80	2		T507	1		T509	12
all_values[22]	3522	1			T80	1		T509	8		T405	21
all_values[23]	3693	1			T80	7		T507	1		T509	7
all_values[24]	3451	1			T80	2		T507	1		T509	10
all_values[25]	3641	1			T80	3		T509	10		T405	17
all_values[26]	3575	1			T80	1		T507	1		T509	16
all_values[27]	3661	1			T80	3		T507	3		T509	9
all_values[28]	3444	1			T80	2		T507	2		T509	9
all_values[29]	3597	1			T80	6		T507	1		T509	13
all_values[30]	3646	1			T80	3		T507	2		T509	12
all_values[31]	3493	1			T80	2		T507	3		T509	16
all_values[32]	3605	1			T80	6		T507	2		T509	17
all_values[33]	3562	1			T80	3		T507	3		T509	15
all_values[34]	3604	1			T80	2		T507	2		T509	16
all_values[35]	3523	1			T80	2		T507	4		T509	14
all_values[36]	3527	1			T507	2		T509	10		T405	22
all_values[37]	3482	1			T80	6		T507	2		T509	14
all_values[38]	3526	1			T80	4		T507	1		T509	9
all_values[39]	3568	1			T80	5		T507	3		T509	14
all_values[40]	3516	1			T80	2		T507	1		T509	5
all_values[41]	3610	1			T80	5		T509	10		T405	18
all_values[42]	3557	1			T80	3		T507	1		T509	8
all_values[43]	3440	1			T80	3		T507	1		T509	13
all_values[44]	3587	1			T80	6		T507	2		T509	10
all_values[45]	3648	1			T80	5		T507	2		T509	18
all_values[46]	3583	1			T80	3		T507	4		T509	11
all_values[47]	3631	1			T80	2		T507	2		T509	14
all_values[48]	3599	1			T80	1		T507	3		T509	7
all_values[49]	3558	1			T80	6		T507	3		T509	16
all_values[50]	3614	1			T80	3		T507	4		T509	17
all_values[51]	3525	1			T80	1		T509	4		T405	21
all_values[52]	3566	1			T80	2		T507	2		T509	14
all_values[53]	3501	1			T80	3		T507	3		T509	13
all_values[54]	3485	1			T80	3		T507	2		T509	11
all_values[55]	3590	1			T80	3		T507	2		T509	7
all_values[56]	3546	1			T80	6		T507	1		T509	15
all_values[57]	3602	1			T80	2		T507	1		T509	6
all_values[58]	3499	1			T80	4		T507	5		T509	16
all_values[59]	3652	1			T80	4		T507	2		T509	12
all_values[60]	3574	1			T80	2		T507	4		T509	17
all_values[61]	3613	1			T80	2		T507	1		T509	9
all_values[62]	3637	1			T80	2		T507	3		T509	12
all_values[63]	3586	1			T80	3		T509	4		T405	13