Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141528	1			T76	12		T77	3		T78	5
values[2]	9847	1			T158	1		T225	1		T423	132
values[3]	3828	1			T423	37		T539	1		T542	3
values[4]	2140	1			T423	25		T539	5		T542	14
values[5]	1309	1			T423	25		T539	3		T542	10
values[6]	932	1			T423	5		T539	5		T542	10
values[7]	809	1			T539	8		T542	6		T796	1
values[8]	574	1			T539	2		T542	11		T796	1
values[9]	497	1			T539	2		T542	7		T796	1
values[10]	424	1			T539	4		T542	5		T796	1
values[11]	400	1			T539	4		T542	12		T796	1
values[12]	360	1			T539	1		T542	8		T796	1
values[13]	316	1			T539	2		T542	5		T796	1
values[14]	293	1			T539	7		T542	6		T796	1
values[15]	311	1			T539	3		T542	3		T796	1
values[16]	302	1			T539	1		T542	8		T796	1
values[17]	318	1			T539	3		T542	4		T796	1
values[18]	328	1			T539	1		T542	13		T796	1
values[19]	290	1			T539	1		T542	7		T796	1
values[20]	311	1			T539	3		T542	9		T796	1
values[21]	342	1			T539	5		T542	10		T796	1
values[22]	366	1			T539	12		T542	5		T796	1
values[23]	299	1			T539	6		T542	6		T796	1
values[24]	293	1			T539	5		T542	5		T796	1
values[25]	333	1			T539	10		T542	15		T796	1
values[26]	317	1			T539	5		T542	4		T796	1
values[27]	258	1			T539	2		T542	3		T796	1
values[28]	273	1			T539	1		T542	4		T796	1
values[29]	262	1			T539	2		T542	3		T796	1
values[30]	282	1			T539	3		T542	6		T796	1
values[31]	302	1			T539	2		T542	4		T796	1
values[32]	338	1			T539	2		T542	6		T796	1
values[33]	312	1			T539	3		T542	22		T796	1
values[34]	334	1			T539	14		T542	16		T796	1
values[35]	294	1			T539	16		T542	3		T796	1
values[36]	283	1			T539	7		T542	3		T796	1
values[37]	303	1			T539	2		T542	7		T796	2
values[38]	305	1			T539	2		T542	4		T796	1
values[39]	243	1			T539	1		T542	5		T796	1
values[40]	339	1			T539	1		T542	4		T796	1
values[41]	274	1			T539	3		T542	3		T796	1
values[42]	240	1			T539	4		T542	14		T796	1
values[43]	274	1			T539	4		T542	13		T796	1
values[44]	311	1			T539	5		T542	9		T796	1
values[45]	317	1			T539	6		T542	13		T796	1
values[46]	303	1			T539	8		T542	3		T796	1
values[47]	309	1			T539	3		T542	4		T796	1
values[48]	309	1			T539	3		T542	6		T796	1
values[49]	284	1			T539	7		T542	7		T796	1
values[50]	305	1			T539	2		T542	6		T796	1
values[51]	225	1			T539	6		T542	8		T796	1
values[52]	317	1			T539	4		T542	11		T796	1
values[53]	286	1			T539	3		T542	6		T796	1
values[54]	302	1			T539	2		T542	7		T796	1
values[55]	271	1			T539	2		T542	8		T796	1
values[56]	236	1			T539	1		T542	5		T796	1
values[57]	217	1			T539	1		T542	3		T796	1
values[58]	248	1			T539	3		T542	6		T796	1
values[59]	230	1			T539	3		T542	7		T796	1
values[60]	238	1			T539	2		T542	4		T796	1
values[61]	222	1			T539	3		T542	3		T796	1
values[62]	208	1			T539	8		T542	7		T796	1
values[63]	208	1			T539	24		T542	3		T796	1
values[64]	213	1			T539	29		T542	11		T796	1
values[65]	188	1			T539	19		T542	13		T796	1
values[66]	215	1			T539	7		T542	27		T796	1
values[67]	202	1			T539	19		T542	14		T796	1
values[68]	172	1			T539	7		T542	2		T796	1
values[69]	173	1			T539	9		T796	1		T800	1
values[70]	154	1			T539	17		T796	1		T800	1
values[71]	139	1			T539	17		T796	1		T800	1
values[72]	130	1			T539	6		T796	1		T800	1
values[73]	109	1			T539	7		T796	1		T800	1
values[74]	84	1			T796	1		T800	1		T787	1
values[75]	92	1			T796	1		T800	1		T787	1
values[76]	105	1			T796	1		T800	1		T787	1
values[77]	92	1			T796	1		T800	1		T787	1
values[78]	86	1			T796	1		T800	1		T787	1
values[79]	85	1			T796	1		T800	1		T787	1
values[80]	96	1			T796	1		T800	1		T787	1
values[81]	97	1			T796	1		T800	1		T787	1
values[82]	85	1			T796	1		T800	1		T787	2
values[83]	81	1			T796	1		T800	1		T787	1
values[84]	106	1			T796	1		T800	1		T787	1
values[85]	92	1			T796	1		T800	1		T787	1
values[86]	79	1			T796	1		T800	1		T787	1
values[87]	82	1			T796	1		T800	1		T787	1
values[88]	95	1			T796	1		T800	1		T787	1
values[89]	97	1			T796	1		T800	1		T787	1
values[90]	91	1			T796	1		T800	3		T787	1
values[91]	88	1			T796	1		T800	3		T787	1
values[92]	86	1			T796	1		T800	3		T787	1
values[93]	71	1			T796	1		T800	4		T787	1
values[94]	90	1			T796	2		T800	6		T787	1
values[95]	84	1			T796	1		T800	5		T787	1
values[96]	94	1			T796	1		T800	6		T787	1
values[97]	96	1			T796	3		T800	1		T787	1
values[98]	91	1			T796	1		T800	3		T787	1
values[99]	92	1			T796	1		T800	4		T787	1
values[100]	100	1			T796	1		T800	4		T787	1
values[101]	89	1			T796	1		T800	2		T787	1
values[102]	100	1			T796	1		T800	2		T787	1
values[103]	87	1			T796	1		T800	2		T787	1
values[104]	87	1			T796	1		T800	1		T787	1
values[105]	73	1			T796	3		T800	1		T787	1
values[106]	102	1			T796	6		T800	3		T787	1
values[107]	90	1			T796	1		T800	1		T787	1
values[108]	93	1			T796	1		T800	1		T787	1
values[109]	96	1			T796	3		T800	2		T787	1
values[110]	90	1			T796	1		T800	1		T787	1
values[111]	100	1			T796	4		T800	3		T787	1
values[112]	93	1			T796	2		T800	4		T787	1
values[113]	85	1			T796	4		T800	2		T787	1
values[114]	76	1			T796	1		T800	1		T787	2
values[115]	99	1			T796	3		T800	1		T787	4
values[116]	76	1			T796	2		T800	1		T787	2
values[117]	82	1			T796	3		T800	2		T787	4
values[118]	70	1			T796	3		T800	1		T787	1
values[119]	89	1			T796	1		T800	1		T787	2
values[120]	77	1			T796	1		T800	1		T787	2
values[121]	83	1			T796	6		T800	1		T787	5
values[122]	86	1			T796	3		T800	3		T787	2
values[123]	76	1			T796	2		T800	1		T787	1
values[124]	63	1			T796	2		T800	5		T787	2
values[125]	85	1			T796	2		T800	1		T787	4
values[126]	145	1			T796	1		T800	4		T787	2
values[127]	912	1			T796	30		T800	38		T787	36
values[128]	7559	1			T796	258		T800	304		T787	305