Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.14 95.59 93.98 95.45 94.77 97.53 99.53


Total tests in report: 2877
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
39.54 39.54 44.96 44.96 42.98 42.98 31.62 31.62 57.85 57.85 59.44 59.44 0.39 0.39 /workspace/coverage/default/59.chip_sw_all_escalation_resets.2599044104
50.23 10.69 55.22 10.27 57.74 14.76 35.00 3.38 69.35 11.51 82.52 23.08 1.55 1.16 /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.1413634376
57.75 7.52 63.11 7.88 61.44 3.69 37.44 2.44 69.70 0.34 82.52 0.00 32.30 30.75 /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.3495718308
63.89 6.14 75.64 12.53 70.00 8.57 41.63 4.19 81.27 11.58 82.52 0.00 32.30 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_0.160404758
67.95 4.06 75.64 0.00 70.00 0.00 41.63 0.00 81.27 0.00 82.52 0.00 56.66 24.36 /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.553752586
71.40 3.45 81.74 6.11 74.37 4.37 45.63 4.00 83.29 2.01 86.71 4.20 56.66 0.00 /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2484158663
73.90 2.50 84.24 2.49 77.38 3.01 52.24 6.61 85.65 2.36 87.24 0.52 56.66 0.00 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1136125883
75.95 2.05 84.24 0.00 77.38 0.00 52.24 0.00 85.65 0.00 87.24 0.00 68.96 12.30 /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.401168408
77.93 1.98 86.75 2.51 79.39 2.01 54.52 2.28 87.38 1.73 90.38 3.15 69.16 0.20 /workspace/coverage/default/2.chip_jtag_csr_rw.2385386876
79.90 1.97 86.75 0.00 79.39 0.00 66.36 11.85 87.38 0.00 90.38 0.00 69.16 0.00 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1499801194
81.86 1.96 86.78 0.02 80.08 0.69 68.37 2.01 87.46 0.08 90.38 0.00 78.10 8.94 /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.3844409120
83.32 1.46 87.06 0.29 80.23 0.15 76.33 7.96 87.63 0.18 90.56 0.17 78.10 0.00 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.4026978114
84.54 1.22 87.06 0.00 80.23 0.00 76.33 0.00 87.63 0.00 90.56 0.00 85.42 7.32 /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.170183680
85.60 1.06 88.32 1.26 82.17 1.94 77.29 0.96 89.48 1.85 90.91 0.35 85.42 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.797719483
86.61 1.01 89.60 1.28 83.26 1.09 79.69 2.40 90.75 1.27 90.91 0.00 85.42 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_20.645382622
87.34 0.74 89.97 0.37 83.36 0.10 79.70 0.01 90.86 0.11 94.76 3.85 85.42 0.00 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3164847629
88.05 0.70 89.97 0.00 83.36 0.00 79.70 0.00 90.86 0.00 94.76 0.00 89.65 4.23 /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.1277847515
88.70 0.66 90.76 0.78 84.18 0.82 81.39 1.69 91.44 0.58 94.76 0.00 89.71 0.06 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3069744802
89.31 0.61 90.78 0.02 84.21 0.04 83.17 1.78 91.44 0.00 94.76 0.00 91.51 1.80 /workspace/coverage/default/0.chip_sw_alert_test.2433024613
89.89 0.58 90.79 0.01 87.25 3.03 83.17 0.00 91.44 0.00 94.76 0.00 91.92 0.41 /workspace/coverage/cover_reg_top/29.chip_tl_errors.2916457474
90.44 0.56 91.81 1.02 88.25 1.00 83.57 0.40 92.34 0.90 94.76 0.00 91.92 0.00 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3268505232
90.93 0.49 91.81 0.00 88.25 0.00 83.57 0.00 92.34 0.00 94.76 0.00 94.88 2.96 /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1655642996
91.34 0.41 92.20 0.39 88.54 0.29 85.03 1.45 92.65 0.31 94.76 0.00 94.88 0.00 /workspace/coverage/default/1.chip_jtag_csr_rw.2955916762
91.69 0.34 92.21 0.01 88.55 0.01 87.07 2.05 92.65 0.00 94.76 0.00 94.88 0.00 /workspace/coverage/default/2.chip_sw_edn_auto_mode.1752091377
92.00 0.32 92.21 0.00 88.65 0.11 87.07 0.00 92.65 0.00 94.76 0.00 96.66 1.79 /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2468260360
92.31 0.31 92.61 0.40 89.01 0.35 87.27 0.19 93.05 0.41 95.28 0.52 96.66 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2128215905
92.61 0.29 93.34 0.73 89.03 0.03 87.52 0.25 93.05 0.00 95.28 0.00 97.40 0.74 /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1952092660
92.85 0.24 93.82 0.47 89.45 0.42 87.68 0.16 93.47 0.41 95.28 0.00 97.40 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_10.2367326346
93.09 0.24 93.82 0.00 89.45 0.00 89.11 1.43 93.47 0.00 95.28 0.00 97.40 0.00 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3933680625
93.26 0.17 93.93 0.12 89.53 0.07 89.52 0.41 93.54 0.07 95.63 0.35 97.40 0.00 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3245689446
93.41 0.15 93.94 0.01 89.59 0.06 90.12 0.60 93.55 0.01 95.80 0.17 97.45 0.05 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1223357506
93.56 0.15 94.15 0.21 89.91 0.32 90.47 0.35 93.55 0.00 95.80 0.00 97.45 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.514672442
93.69 0.14 94.15 0.00 90.06 0.15 90.47 0.00 93.55 0.00 95.80 0.00 98.13 0.68 /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2690163245
93.82 0.13 94.21 0.07 90.25 0.19 90.58 0.10 93.61 0.06 96.15 0.35 98.13 0.00 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1412014277
93.94 0.12 94.21 0.00 90.94 0.69 90.58 0.00 93.61 0.00 96.15 0.00 98.13 0.00 /workspace/coverage/cover_reg_top/4.chip_tl_errors.3243929263
94.05 0.11 94.21 0.00 90.94 0.01 91.25 0.67 93.61 0.00 96.15 0.00 98.13 0.00 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2260973210
94.15 0.10 94.21 0.00 90.94 0.00 91.86 0.61 93.61 0.00 96.15 0.00 98.13 0.00 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.4292444648
94.24 0.09 94.21 0.00 91.19 0.24 91.88 0.02 93.89 0.28 96.15 0.00 98.13 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3151827287
94.33 0.08 94.25 0.03 91.20 0.01 92.33 0.45 93.90 0.01 96.15 0.00 98.13 0.00 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3824067009
94.41 0.08 94.34 0.09 91.36 0.16 92.45 0.12 94.00 0.11 96.15 0.00 98.13 0.00 /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2175054223
94.48 0.07 94.34 0.00 91.37 0.01 92.89 0.44 94.00 0.00 96.15 0.00 98.13 0.00 /workspace/coverage/default/63.chip_sw_all_escalation_resets.402057858
94.55 0.07 94.34 0.00 91.37 0.00 93.33 0.43 94.00 0.00 96.15 0.00 98.13 0.00 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1271583577
94.62 0.07 94.34 0.00 91.43 0.06 93.33 0.01 94.01 0.01 96.50 0.35 98.13 0.00 /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2577358966
94.69 0.07 94.37 0.03 91.46 0.03 93.47 0.14 94.04 0.02 96.68 0.17 98.13 0.00 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1538939510
94.75 0.06 94.37 0.00 91.63 0.17 93.47 0.00 94.23 0.19 96.68 0.00 98.13 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.56371162
94.80 0.05 94.43 0.07 91.78 0.15 93.47 0.00 94.33 0.10 96.68 0.00 98.13 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.510348222
94.85 0.05 94.43 0.00 92.08 0.30 93.47 0.00 94.33 0.00 96.68 0.00 98.13 0.00 /workspace/coverage/cover_reg_top/12.chip_tl_errors.3229344971
94.90 0.05 94.53 0.10 92.08 0.00 93.64 0.17 94.34 0.02 96.68 0.00 98.13 0.00 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3307503687
94.94 0.04 94.54 0.01 92.09 0.01 93.64 0.00 94.37 0.02 96.85 0.17 98.14 0.01 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1825209904
94.98 0.04 94.54 0.00 92.27 0.18 93.64 0.00 94.42 0.05 96.85 0.00 98.14 0.00 /workspace/coverage/cover_reg_top/61.xbar_stress_all.1861995541
95.01 0.04 94.54 0.00 92.27 0.00 93.85 0.22 94.42 0.00 96.85 0.00 98.14 0.00 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3121450821
95.05 0.04 94.55 0.01 92.28 0.01 93.86 0.01 94.43 0.01 97.03 0.17 98.16 0.01 /workspace/coverage/default/39.chip_sw_all_escalation_resets.479494011
95.09 0.04 94.55 0.01 92.29 0.01 93.87 0.01 94.43 0.01 97.20 0.17 98.17 0.01 /workspace/coverage/default/60.chip_sw_all_escalation_resets.3987175703
95.12 0.04 94.56 0.01 92.30 0.01 93.87 0.00 94.44 0.01 97.38 0.17 98.18 0.01 /workspace/coverage/default/23.chip_sw_all_escalation_resets.368730189
95.16 0.04 94.56 0.00 92.30 0.00 94.08 0.21 94.44 0.00 97.38 0.00 98.18 0.00 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1507990866
95.19 0.04 94.56 0.00 92.30 0.00 94.12 0.04 94.44 0.00 97.55 0.17 98.18 0.00 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3361277303
95.22 0.03 94.56 0.00 92.30 0.00 94.12 0.00 94.44 0.00 97.55 0.00 98.36 0.18 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3065960048
95.25 0.03 94.56 0.00 92.48 0.17 94.12 0.00 94.44 0.00 97.55 0.00 98.36 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_0.3159875098
95.28 0.03 94.56 0.00 92.48 0.00 94.29 0.17 94.44 0.00 97.55 0.00 98.36 0.00 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1050138929
95.31 0.03 94.56 0.00 92.48 0.00 94.46 0.17 94.44 0.00 97.55 0.00 98.36 0.00 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1538540888
95.33 0.03 94.60 0.05 92.53 0.05 94.47 0.01 94.49 0.05 97.55 0.00 98.36 0.00 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.389171221
95.36 0.03 94.60 0.00 92.54 0.01 94.62 0.15 94.49 0.00 97.55 0.00 98.36 0.00 /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.3743840669
95.38 0.02 94.67 0.07 92.59 0.05 94.62 0.00 94.52 0.03 97.55 0.00 98.36 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.2426194028
95.41 0.02 94.73 0.07 92.62 0.03 94.62 0.01 94.57 0.05 97.55 0.00 98.36 0.00 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3191676784
95.43 0.02 94.80 0.07 92.67 0.05 94.63 0.01 94.59 0.02 97.55 0.00 98.36 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.216046723
95.46 0.02 94.83 0.03 92.71 0.05 94.68 0.04 94.61 0.02 97.55 0.00 98.36 0.00 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.498731739
95.48 0.02 94.83 0.00 92.85 0.13 94.68 0.01 94.61 0.00 97.55 0.00 98.36 0.00 /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.200564776
95.50 0.02 94.85 0.03 92.89 0.04 94.72 0.04 94.64 0.02 97.55 0.00 98.36 0.00 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3887511927
95.52 0.02 94.85 0.00 92.98 0.10 94.72 0.00 94.65 0.02 97.55 0.00 98.36 0.00 /workspace/coverage/cover_reg_top/65.xbar_stress_all.1158776541
95.54 0.02 94.86 0.01 92.99 0.01 94.79 0.07 94.67 0.02 97.55 0.00 98.36 0.00 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2804628137
95.55 0.02 94.86 0.00 93.00 0.01 94.79 0.00 94.67 0.00 97.55 0.00 98.45 0.09 /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.208741592
95.57 0.02 94.86 0.00 93.00 0.00 94.89 0.10 94.67 0.00 97.55 0.00 98.45 0.00 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3767241838
95.59 0.02 94.86 0.00 93.05 0.05 94.89 0.00 94.67 0.00 97.55 0.00 98.50 0.05 /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.1763736539
95.60 0.01 94.88 0.01 93.08 0.03 94.91 0.03 94.69 0.02 97.55 0.00 98.50 0.00 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.4078078951
95.61 0.01 94.88 0.00 93.11 0.03 94.91 0.00 94.69 0.00 97.55 0.00 98.54 0.05 /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3831898210
95.63 0.01 94.88 0.00 93.19 0.08 94.91 0.00 94.69 0.00 97.55 0.00 98.54 0.00 /workspace/coverage/cover_reg_top/24.chip_tl_errors.1135879230
95.64 0.01 94.88 0.00 93.26 0.07 94.91 0.00 94.69 0.00 97.55 0.00 98.54 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_20.3246896221
95.65 0.01 94.88 0.01 93.27 0.01 94.95 0.04 94.69 0.01 97.55 0.00 98.55 0.01 /workspace/coverage/default/49.chip_sw_all_escalation_resets.1108739584
95.66 0.01 94.88 0.00 93.27 0.00 95.02 0.07 94.69 0.00 97.55 0.00 98.55 0.00 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3946956008
95.67 0.01 94.88 0.00 93.28 0.01 95.02 0.00 94.69 0.00 97.55 0.00 98.61 0.06 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.1279029933
95.68 0.01 94.88 0.00 93.33 0.05 95.02 0.00 94.71 0.02 97.55 0.00 98.61 0.00 /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.937309918
95.69 0.01 94.88 0.00 93.39 0.06 95.02 0.00 94.71 0.00 97.55 0.00 98.61 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_0.3930125526
95.70 0.01 94.89 0.01 93.40 0.01 95.05 0.03 94.71 0.00 97.55 0.00 98.61 0.00 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2780090190
95.71 0.01 94.92 0.02 93.41 0.01 95.06 0.01 94.73 0.02 97.55 0.00 98.61 0.00 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2129700709
95.72 0.01 94.92 0.00 93.46 0.05 95.06 0.00 94.73 0.00 97.55 0.00 98.61 0.00 /workspace/coverage/cover_reg_top/0.chip_tl_errors.3606105394
95.73 0.01 94.92 0.00 93.47 0.01 95.06 0.00 94.73 0.00 97.55 0.00 98.66 0.05 /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.1727883344
95.74 0.01 94.94 0.02 93.47 0.01 95.06 0.01 94.74 0.02 97.55 0.00 98.66 0.00 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1424391441
95.75 0.01 94.96 0.02 93.48 0.01 95.06 0.01 94.76 0.02 97.55 0.00 98.66 0.00 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3538296496
95.75 0.01 94.96 0.00 93.50 0.02 95.08 0.02 94.76 0.00 97.55 0.00 98.67 0.01 /workspace/coverage/default/18.chip_sw_all_escalation_resets.95386439
95.76 0.01 94.96 0.00 93.52 0.02 95.11 0.03 94.76 0.00 97.55 0.00 98.67 0.00 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.605274753
95.77 0.01 94.96 0.00 93.52 0.00 95.15 0.04 94.76 0.00 97.55 0.00 98.67 0.00 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.645788006
95.77 0.01 94.96 0.00 93.55 0.04 95.15 0.00 94.76 0.00 97.55 0.00 98.67 0.00 /workspace/coverage/cover_reg_top/48.xbar_stress_all.2202933397
95.78 0.01 94.96 0.00 93.55 0.00 95.19 0.04 94.76 0.00 97.55 0.00 98.67 0.00 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.578905270
95.79 0.01 94.96 0.00 93.59 0.04 95.19 0.00 94.76 0.00 97.55 0.00 98.67 0.00 /workspace/coverage/default/2.chip_sw_gpio.489526760
95.79 0.01 94.96 0.00 93.59 0.00 95.19 0.00 94.76 0.00 97.55 0.00 98.71 0.04 /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2109816322
95.80 0.01 94.96 0.00 93.59 0.00 95.22 0.03 94.76 0.00 97.55 0.00 98.71 0.00 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3366799487
95.80 0.01 94.96 0.00 93.62 0.03 95.22 0.00 94.76 0.00 97.55 0.00 98.71 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_10.994105211
95.81 0.01 94.96 0.00 93.63 0.01 95.22 0.00 94.76 0.00 97.55 0.00 98.73 0.02 /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2836350831
95.81 0.01 94.96 0.00 93.65 0.02 95.22 0.00 94.76 0.00 97.55 0.00 98.74 0.01 /workspace/coverage/cover_reg_top/23.chip_tl_errors.2215397780
95.82 0.01 94.96 0.00 93.65 0.00 95.25 0.03 94.76 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/0.chip_sw_usbdev_config_host.1188323116
95.82 0.01 94.96 0.00 93.67 0.03 95.25 0.00 94.76 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3737596232
95.83 0.01 94.96 0.00 93.67 0.00 95.28 0.03 94.76 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3491885588
95.83 0.01 94.96 0.00 93.70 0.02 95.28 0.00 94.76 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.449244822
95.84 0.01 94.96 0.00 93.70 0.00 95.30 0.02 94.76 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.141133728
95.84 0.01 94.97 0.01 93.71 0.01 95.30 0.00 94.76 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/0.chip_jtag_csr_rw.3687969067
95.84 0.01 94.99 0.01 93.72 0.01 95.30 0.00 94.76 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/1.chip_sw_pattgen_ios.1358156419
95.85 0.01 94.99 0.00 93.73 0.01 95.30 0.00 94.77 0.01 97.55 0.00 98.75 0.01 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3474417548
95.85 0.01 94.99 0.00 93.74 0.01 95.30 0.00 94.77 0.00 97.55 0.00 98.77 0.01 /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.2945484323
95.86 0.01 94.99 0.00 93.76 0.02 95.30 0.00 94.77 0.00 97.55 0.00 98.77 0.00 /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.3162785719
95.86 0.01 94.99 0.00 93.76 0.00 95.31 0.01 94.77 0.00 97.55 0.00 98.78 0.01 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2367185017
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96.05 0.01 95.02 0.00 93.98 0.00 95.44 0.01 94.77 0.00 97.55 0.00 99.53 0.00 /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.584846692
96.05 0.01 95.02 0.00 93.98 0.00 95.44 0.01 94.77 0.00 97.55 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_edn_boot_mode.4031866993
96.05 0.01 95.02 0.00 93.98 0.00 95.44 0.01 94.77 0.00 97.55 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.4101305302
96.05 0.01 95.02 0.00 93.98 0.00 95.45 0.01 94.77 0.00 97.55 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.380104261
96.05 0.01 95.02 0.00 93.98 0.00 95.45 0.01 94.77 0.00 97.55 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3662480943


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3390140241
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1310823584
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1129565248
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2072570176
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3520051946
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2442037886
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1700353934
/workspace/coverage/cover_reg_top/0.xbar_error_random.80312727
/workspace/coverage/cover_reg_top/0.xbar_random.1516276206
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.576824313
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2717269104
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1279571680
/workspace/coverage/cover_reg_top/0.xbar_same_source.158723758
/workspace/coverage/cover_reg_top/0.xbar_smoke.2372279786
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2576986421
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2568376024
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2777643821
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2558311903
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1971204286
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2660390450
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2226699256
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.4088330879
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.4204054381
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1642837714
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.4058709425
/workspace/coverage/cover_reg_top/1.chip_csr_rw.162658289
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.4265384435
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2198763228
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.713795092
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2392993748
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2349460116
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2073808399
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.4003623706
/workspace/coverage/cover_reg_top/1.xbar_error_random.839367559
/workspace/coverage/cover_reg_top/1.xbar_random.4141591136
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1163929387
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.4121627332
/workspace/coverage/cover_reg_top/1.xbar_same_source.2258003658
/workspace/coverage/cover_reg_top/1.xbar_smoke.3746993286
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1558738123
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1716552959
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1830269304
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3330584027
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1857872368
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.769756900
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.855538874
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.4256064955
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3116199425
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1724106547
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1432762749
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.434672471
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.4171439393
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.760564459
/workspace/coverage/cover_reg_top/10.xbar_error_random.955358446
/workspace/coverage/cover_reg_top/10.xbar_random.958555501
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2047083317
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.673951766
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1396113391
/workspace/coverage/cover_reg_top/10.xbar_same_source.3505478690
/workspace/coverage/cover_reg_top/10.xbar_smoke.1060341372
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1079163542
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2816365270
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.546506164
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2386460658
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1264224698
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.886384480
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.65446416
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2569112579
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1464255384
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2092682400
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.84994465
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3198088442
/workspace/coverage/cover_reg_top/11.xbar_error_random.2075327939
/workspace/coverage/cover_reg_top/11.xbar_random.416915318
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3804293719
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.835897819
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1226400628
/workspace/coverage/cover_reg_top/11.xbar_same_source.2552465084
/workspace/coverage/cover_reg_top/11.xbar_smoke.3942900552
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1995985449
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3857867616
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.563850788
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1908743735
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1845092326
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1042705797
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3288144420
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.4224997623
/workspace/coverage/cover_reg_top/12.chip_csr_rw.4094178460
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.155710516
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3663834338
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.963522412
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1396440807
/workspace/coverage/cover_reg_top/12.xbar_error_random.886350503
/workspace/coverage/cover_reg_top/12.xbar_random.3553957223
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3997795425
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2821301250
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.4234848704
/workspace/coverage/cover_reg_top/12.xbar_same_source.2510063733
/workspace/coverage/cover_reg_top/12.xbar_smoke.2804573365
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.565601759
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.175729103
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2978122585
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2994541130
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1656420241
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2646016773
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2096429203
/workspace/coverage/cover_reg_top/13.chip_csr_rw.644301780
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3508175050
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3839509617
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3450151336
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2813127630
/workspace/coverage/cover_reg_top/13.xbar_error_random.1727263401
/workspace/coverage/cover_reg_top/13.xbar_random.927426935
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.187296170
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1936598267
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.576583498
/workspace/coverage/cover_reg_top/13.xbar_same_source.789883928
/workspace/coverage/cover_reg_top/13.xbar_smoke.3872924901
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.272784043
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3132755485
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1189566097
/workspace/coverage/cover_reg_top/13.xbar_stress_all.1613754051
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3232560290
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3985510050
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.4072521708
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1882973131
/workspace/coverage/cover_reg_top/14.chip_csr_rw.278077594
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2281909972
/workspace/coverage/cover_reg_top/14.chip_tl_errors.3010890881
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.3267751548
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2504842654
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.953775823
/workspace/coverage/cover_reg_top/14.xbar_error_random.642627091
/workspace/coverage/cover_reg_top/14.xbar_random.3624992866
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1690679817
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3332754427
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3572447638
/workspace/coverage/cover_reg_top/14.xbar_same_source.1329589743
/workspace/coverage/cover_reg_top/14.xbar_smoke.2018105565
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2727598704
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1764883883
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3093385649
/workspace/coverage/cover_reg_top/14.xbar_stress_all.1146689339
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.34087261
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3306850627
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.539821937
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2539254308
/workspace/coverage/cover_reg_top/15.chip_csr_rw.3540724839
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.3946406615
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.4222649730
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1968919273
/workspace/coverage/cover_reg_top/15.xbar_error_random.1040226768
/workspace/coverage/cover_reg_top/15.xbar_random.3189753212
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.740750245
/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.3972349210
/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.3696820375
/workspace/coverage/cover_reg_top/15.xbar_same_source.438198832
/workspace/coverage/cover_reg_top/15.xbar_smoke.3730041187
/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.2654534838
/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.1272029748
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.4145696443
/workspace/coverage/cover_reg_top/15.xbar_stress_all.184360857
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.3729336048
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.429835829
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3174219992
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2502040790
/workspace/coverage/cover_reg_top/16.chip_csr_rw.1635293401
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.626923674
/workspace/coverage/cover_reg_top/16.chip_tl_errors.3937578203
/workspace/coverage/cover_reg_top/16.xbar_access_same_device.2916047308
/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.4093239671
/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1268350357
/workspace/coverage/cover_reg_top/16.xbar_error_random.3296816964
/workspace/coverage/cover_reg_top/16.xbar_random.2106224856
/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.1645543028
/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.3198221995
/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.61695937
/workspace/coverage/cover_reg_top/16.xbar_same_source.103718025
/workspace/coverage/cover_reg_top/16.xbar_smoke.2577531370
/workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.2651229444
/workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.250198161
/workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1370355227
/workspace/coverage/cover_reg_top/16.xbar_stress_all.101554878
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.801365717
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2843484975
/workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1078649101
/workspace/coverage/cover_reg_top/17.chip_csr_rw.3992640565
/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.3124029158
/workspace/coverage/cover_reg_top/17.chip_tl_errors.3796491806
/workspace/coverage/cover_reg_top/17.xbar_access_same_device.3641972947
/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3220029600
/workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.944093726
/workspace/coverage/cover_reg_top/17.xbar_error_random.796402725
/workspace/coverage/cover_reg_top/17.xbar_random.1552513762
/workspace/coverage/cover_reg_top/17.xbar_random_large_delays.2449225011
/workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.2342827733
/workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2043625373
/workspace/coverage/cover_reg_top/17.xbar_same_source.4011741838
/workspace/coverage/cover_reg_top/17.xbar_smoke.4276628762
/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.2533936707
/workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1813228274
/workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.294702830
/workspace/coverage/cover_reg_top/17.xbar_stress_all.4127445886
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.2522976413
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.3187289766
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.3696264129
/workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.1739696449
/workspace/coverage/cover_reg_top/18.chip_csr_rw.1528594298
/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3433851642
/workspace/coverage/cover_reg_top/18.xbar_access_same_device.1260030748
/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1866842430
/workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.3463355298
/workspace/coverage/cover_reg_top/18.xbar_error_random.886883168
/workspace/coverage/cover_reg_top/18.xbar_random.2918886471
/workspace/coverage/cover_reg_top/18.xbar_random_large_delays.473287269
/workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1923522136
/workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.1219526423
/workspace/coverage/cover_reg_top/18.xbar_same_source.2042679270
/workspace/coverage/cover_reg_top/18.xbar_smoke.831343680
/workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.2956739876
/workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.1515544238
/workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.3055983700
/workspace/coverage/cover_reg_top/18.xbar_stress_all.2582520120
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.4124538741
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.4013772266
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3890921177
/workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.760731865
/workspace/coverage/cover_reg_top/19.chip_csr_rw.290833857
/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.898439393
/workspace/coverage/cover_reg_top/19.chip_tl_errors.1954986612
/workspace/coverage/cover_reg_top/19.xbar_access_same_device.840721762
/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1359744483
/workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2079858009
/workspace/coverage/cover_reg_top/19.xbar_error_random.733951338
/workspace/coverage/cover_reg_top/19.xbar_random.3112465922
/workspace/coverage/cover_reg_top/19.xbar_random_large_delays.3070867290
/workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.1758746181
/workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.131496337
/workspace/coverage/cover_reg_top/19.xbar_same_source.115027978
/workspace/coverage/cover_reg_top/19.xbar_smoke.133417350
/workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.952987921
/workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2400812550
/workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2779209628
/workspace/coverage/cover_reg_top/19.xbar_stress_all.393843388
/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.4273215451
/workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.3972296040
/workspace/coverage/cover_reg_top/2.chip_csr_aliasing.1862501029
/workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.2395939341
/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2183107844
/workspace/coverage/cover_reg_top/2.chip_csr_rw.2371130824
/workspace/coverage/cover_reg_top/2.chip_prim_tl_access.1157248734
/workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.755469799
/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3694785514
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/workspace/coverage/default/73.chip_sw_all_escalation_resets.291902147
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1634928438
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2962039704
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2911702361
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2929821449
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3008766045
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3468465290
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.514644143
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2259907178
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2419901964
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3714419849
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2645956510
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1900422533
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.391256615
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2646060556
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1658451895
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1578950727
/workspace/coverage/default/81.chip_sw_all_escalation_resets.97291499
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2820953285
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3369950100
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3324061013
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1813521770
/workspace/coverage/default/84.chip_sw_all_escalation_resets.4004736644
/workspace/coverage/default/85.chip_sw_all_escalation_resets.1839815050
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2351140843
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3775742614
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2893549903
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2855394589
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3347215219
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1224630952
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3601202924
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.828537669
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1483824360
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3683187457
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2282212884
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3967313306
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3002635026
/workspace/coverage/default/91.chip_sw_all_escalation_resets.742484715
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3645983815
/workspace/coverage/default/94.chip_sw_all_escalation_resets.36957011
/workspace/coverage/default/95.chip_sw_all_escalation_resets.588512508
/workspace/coverage/default/97.chip_sw_all_escalation_resets.2448826054
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1666344517
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1578036469
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1432690531
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.11773662
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3246148347
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3712796204
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3542172179
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.4122357782
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4202974930
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1694995944




Total test records in report: 2877
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1507990866 Jun 27 08:36:13 PM PDT 24 Jun 27 08:54:42 PM PDT 24 6458330272 ps
T5 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2237714747 Jun 27 08:24:18 PM PDT 24 Jun 27 08:27:52 PM PDT 24 2351060689 ps
T6 /workspace/coverage/default/1.chip_sw_hmac_oneshot.219240589 Jun 27 08:27:56 PM PDT 24 Jun 27 08:34:24 PM PDT 24 2510921724 ps
T17 /workspace/coverage/default/59.chip_sw_all_escalation_resets.2599044104 Jun 27 08:51:47 PM PDT 24 Jun 27 09:00:04 PM PDT 24 5482651218 ps
T44 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3535934283 Jun 27 08:23:24 PM PDT 24 Jun 27 08:29:20 PM PDT 24 3857849930 ps
T87 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1508934971 Jun 27 08:28:59 PM PDT 24 Jun 27 08:55:44 PM PDT 24 6631567832 ps
T55 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1136125883 Jun 27 08:27:35 PM PDT 24 Jun 27 09:48:12 PM PDT 24 15859917112 ps
T18 /workspace/coverage/default/4.chip_sw_all_escalation_resets.1431642722 Jun 27 08:45:27 PM PDT 24 Jun 27 08:53:57 PM PDT 24 4791346940 ps
T64 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3824067009 Jun 27 08:20:33 PM PDT 24 Jun 27 08:30:32 PM PDT 24 4312050120 ps
T34 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3245689446 Jun 27 08:25:11 PM PDT 24 Jun 27 08:31:41 PM PDT 24 3535925164 ps
T19 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2367185017 Jun 27 08:53:49 PM PDT 24 Jun 27 09:01:07 PM PDT 24 3425336156 ps
T178 /workspace/coverage/default/10.chip_sw_all_escalation_resets.32336121 Jun 27 08:46:32 PM PDT 24 Jun 27 08:58:41 PM PDT 24 5307500214 ps
T175 /workspace/coverage/default/76.chip_sw_all_escalation_resets.519313582 Jun 27 08:54:37 PM PDT 24 Jun 27 09:03:07 PM PDT 24 4548492088 ps
T56 /workspace/coverage/default/2.rom_e2e_static_critical.2947194125 Jun 27 08:57:28 PM PDT 24 Jun 27 10:16:12 PM PDT 24 16521241740 ps
T202 /workspace/coverage/default/1.chip_sw_all_escalation_resets.1387972977 Jun 27 08:22:38 PM PDT 24 Jun 27 08:33:08 PM PDT 24 4936012704 ps
T218 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.240507390 Jun 27 08:33:19 PM PDT 24 Jun 27 09:05:06 PM PDT 24 8317244180 ps
T159 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1319511093 Jun 27 08:18:25 PM PDT 24 Jun 27 09:52:38 PM PDT 24 27418761000 ps
T183 /workspace/coverage/default/1.chip_sw_flash_crash_alert.56724912 Jun 27 08:31:00 PM PDT 24 Jun 27 08:41:50 PM PDT 24 4369116318 ps
T23 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.797719483 Jun 27 08:33:31 PM PDT 24 Jun 27 08:38:44 PM PDT 24 2508827419 ps
T123 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4126131279 Jun 27 08:18:36 PM PDT 24 Jun 27 08:30:08 PM PDT 24 8222956120 ps
T184 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1223357506 Jun 27 08:18:49 PM PDT 24 Jun 27 08:28:44 PM PDT 24 4566835456 ps
T32 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2961990518 Jun 27 08:19:00 PM PDT 24 Jun 27 09:09:01 PM PDT 24 11864671530 ps
T261 /workspace/coverage/default/0.chip_plic_all_irqs_0.160404758 Jun 27 08:21:58 PM PDT 24 Jun 27 08:40:38 PM PDT 24 5930260360 ps
T181 /workspace/coverage/default/49.chip_sw_all_escalation_resets.1108739584 Jun 27 08:51:21 PM PDT 24 Jun 27 08:58:56 PM PDT 24 5008606886 ps
T292 /workspace/coverage/default/18.chip_sw_all_escalation_resets.95386439 Jun 27 08:48:05 PM PDT 24 Jun 27 08:56:19 PM PDT 24 4208104784 ps
T189 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.225621634 Jun 27 08:37:35 PM PDT 24 Jun 27 08:46:44 PM PDT 24 3653382888 ps
T7 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2804628137 Jun 27 08:19:57 PM PDT 24 Jun 27 08:26:59 PM PDT 24 4582449450 ps
T293 /workspace/coverage/default/0.chip_plic_all_irqs_20.645382622 Jun 27 08:20:16 PM PDT 24 Jun 27 08:33:18 PM PDT 24 5003597270 ps
T182 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1252427450 Jun 27 08:29:03 PM PDT 24 Jun 27 08:42:27 PM PDT 24 4607073688 ps
T20 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1043253376 Jun 27 08:17:55 PM PDT 24 Jun 27 08:32:13 PM PDT 24 6053990816 ps
T251 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.567996411 Jun 27 08:19:58 PM PDT 24 Jun 27 08:25:58 PM PDT 24 4021587340 ps
T349 /workspace/coverage/default/64.chip_sw_all_escalation_resets.477057231 Jun 27 08:52:15 PM PDT 24 Jun 27 09:04:10 PM PDT 24 5653165436 ps
T248 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1538939510 Jun 27 08:17:46 PM PDT 24 Jun 27 08:28:50 PM PDT 24 5215671512 ps
T249 /workspace/coverage/default/58.chip_sw_all_escalation_resets.4138492423 Jun 27 08:52:44 PM PDT 24 Jun 27 09:03:05 PM PDT 24 4654996476 ps
T173 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.4103382196 Jun 27 08:24:28 PM PDT 24 Jun 27 08:44:39 PM PDT 24 6493536512 ps
T262 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3689366819 Jun 27 08:33:57 PM PDT 24 Jun 27 08:39:55 PM PDT 24 3008004322 ps
T29 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3268505232 Jun 27 08:32:12 PM PDT 24 Jun 27 08:37:09 PM PDT 24 3261533191 ps
T59 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1768883358 Jun 27 08:38:27 PM PDT 24 Jun 27 08:40:19 PM PDT 24 2599419795 ps
T65 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.177142337 Jun 27 08:30:46 PM PDT 24 Jun 27 08:42:13 PM PDT 24 5693480250 ps
T273 /workspace/coverage/default/0.chip_sw_kmac_idle.45785231 Jun 27 08:23:36 PM PDT 24 Jun 27 08:28:01 PM PDT 24 3445856728 ps
T35 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1263364760 Jun 27 08:19:46 PM PDT 24 Jun 27 08:26:48 PM PDT 24 3928970984 ps
T128 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3720621762 Jun 27 08:19:44 PM PDT 24 Jun 27 08:23:58 PM PDT 24 2860956600 ps
T116 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2931841446 Jun 27 08:18:44 PM PDT 24 Jun 27 08:25:24 PM PDT 24 3181353112 ps
T317 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2829264976 Jun 27 08:47:21 PM PDT 24 Jun 27 08:54:11 PM PDT 24 4079048162 ps
T1 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.216046723 Jun 27 08:21:30 PM PDT 24 Jun 27 08:29:31 PM PDT 24 5349370832 ps
T21 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.4026978114 Jun 27 08:34:48 PM PDT 24 Jun 27 10:02:30 PM PDT 24 47047876445 ps
T103 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1840315049 Jun 27 08:36:04 PM PDT 24 Jun 27 08:48:24 PM PDT 24 4675895592 ps
T104 /workspace/coverage/default/0.chip_sw_aes_masking_off.3623531864 Jun 27 08:19:27 PM PDT 24 Jun 27 08:23:19 PM PDT 24 3207480434 ps
T105 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2441684273 Jun 27 08:48:24 PM PDT 24 Jun 27 08:54:51 PM PDT 24 4093127210 ps
T106 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.700670210 Jun 27 08:36:24 PM PDT 24 Jun 27 08:42:42 PM PDT 24 4252142760 ps
T107 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4019923386 Jun 27 08:16:00 PM PDT 24 Jun 27 08:27:30 PM PDT 24 4513774034 ps
T57 /workspace/coverage/default/0.rom_e2e_asm_init_rma.1252189293 Jun 27 08:25:53 PM PDT 24 Jun 27 09:31:25 PM PDT 24 14132690739 ps
T108 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3007776503 Jun 27 08:40:18 PM PDT 24 Jun 27 08:49:15 PM PDT 24 4306509314 ps
T68 /workspace/coverage/default/2.rom_volatile_raw_unlock.4228136030 Jun 27 08:43:14 PM PDT 24 Jun 27 08:45:16 PM PDT 24 2398750244 ps
T201 /workspace/coverage/default/0.chip_tap_straps_prod.4195914352 Jun 27 08:18:57 PM PDT 24 Jun 27 08:22:12 PM PDT 24 2427362019 ps
T329 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3307837149 Jun 27 08:20:12 PM PDT 24 Jun 27 08:25:51 PM PDT 24 3821957416 ps
T117 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.605274753 Jun 27 08:35:41 PM PDT 24 Jun 27 08:46:06 PM PDT 24 3967441963 ps
T113 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1154903447 Jun 27 08:31:50 PM PDT 24 Jun 27 09:34:14 PM PDT 24 24570208666 ps
T848 /workspace/coverage/default/0.chip_sw_example_rom.1351972991 Jun 27 08:15:21 PM PDT 24 Jun 27 08:17:13 PM PDT 24 2374314584 ps
T250 /workspace/coverage/default/38.chip_sw_all_escalation_resets.1615746123 Jun 27 08:51:22 PM PDT 24 Jun 27 09:02:34 PM PDT 24 6263334454 ps
T667 /workspace/coverage/default/12.chip_sw_all_escalation_resets.1158592746 Jun 27 08:48:14 PM PDT 24 Jun 27 08:58:52 PM PDT 24 5431918840 ps
T45 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2780090190 Jun 27 08:23:20 PM PDT 24 Jun 27 08:28:27 PM PDT 24 2676150648 ps
T219 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1178261246 Jun 27 08:19:52 PM PDT 24 Jun 27 08:35:08 PM PDT 24 5029153026 ps
T185 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.579100585 Jun 27 08:40:38 PM PDT 24 Jun 27 08:45:25 PM PDT 24 2751976656 ps
T303 /workspace/coverage/default/0.chip_sw_uart_smoketest.1215102159 Jun 27 08:22:10 PM PDT 24 Jun 27 08:25:59 PM PDT 24 2502851086 ps
T125 /workspace/coverage/default/2.chip_sw_edn_auto_mode.1752091377 Jun 27 08:36:57 PM PDT 24 Jun 27 08:58:10 PM PDT 24 4305603764 ps
T263 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1034142437 Jun 27 08:24:13 PM PDT 24 Jun 27 08:48:50 PM PDT 24 13178560081 ps
T286 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1929361052 Jun 27 08:19:23 PM PDT 24 Jun 27 08:26:27 PM PDT 24 3509706280 ps
T226 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1499801194 Jun 27 08:38:34 PM PDT 24 Jun 27 09:22:10 PM PDT 24 13460718660 ps
T304 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2289650149 Jun 27 08:38:56 PM PDT 24 Jun 27 08:43:44 PM PDT 24 2527435250 ps
T118 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3218021861 Jun 27 08:39:23 PM PDT 24 Jun 27 08:50:17 PM PDT 24 4983668186 ps
T264 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1112367166 Jun 27 08:47:55 PM PDT 24 Jun 27 09:45:43 PM PDT 24 17035925420 ps
T305 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.397739397 Jun 27 08:18:55 PM PDT 24 Jun 27 08:24:21 PM PDT 24 2757684968 ps
T427 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3072474870 Jun 27 08:32:08 PM PDT 24 Jun 27 08:49:13 PM PDT 24 5832359840 ps
T124 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1004565 Jun 27 08:32:46 PM PDT 24 Jun 27 08:45:40 PM PDT 24 8214658392 ps
T69 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3308440955 Jun 27 08:23:09 PM PDT 24 Jun 27 09:01:26 PM PDT 24 32811940534 ps
T220 /workspace/coverage/default/1.chip_sw_pattgen_ios.1358156419 Jun 27 08:23:30 PM PDT 24 Jun 27 08:28:36 PM PDT 24 2573027582 ps
T849 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4157557272 Jun 27 08:21:49 PM PDT 24 Jun 27 08:25:03 PM PDT 24 2983609332 ps
T672 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1718064871 Jun 27 08:49:52 PM PDT 24 Jun 27 08:57:05 PM PDT 24 3846060240 ps
T26 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1412014277 Jun 27 08:35:08 PM PDT 24 Jun 27 08:46:26 PM PDT 24 6787743363 ps
T252 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2503573550 Jun 27 08:29:39 PM PDT 24 Jun 27 08:38:32 PM PDT 24 5298949250 ps
T224 /workspace/coverage/default/0.chip_sw_flash_crash_alert.2339068466 Jun 27 08:19:04 PM PDT 24 Jun 27 08:31:14 PM PDT 24 4587979720 ps
T339 /workspace/coverage/default/83.chip_sw_all_escalation_resets.3324061013 Jun 27 08:54:23 PM PDT 24 Jun 27 09:02:06 PM PDT 24 5377925332 ps
T114 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2237668143 Jun 27 08:19:30 PM PDT 24 Jun 27 08:40:38 PM PDT 24 7499056225 ps
T351 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2631808908 Jun 27 08:19:55 PM PDT 24 Jun 27 08:45:04 PM PDT 24 9975081230 ps
T22 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2641922763 Jun 27 08:44:51 PM PDT 24 Jun 27 09:04:21 PM PDT 24 12236251428 ps
T428 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1573361617 Jun 27 08:16:24 PM PDT 24 Jun 27 08:35:07 PM PDT 24 5865062116 ps
T221 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2084358976 Jun 27 08:33:37 PM PDT 24 Jun 27 08:52:02 PM PDT 24 5211785584 ps
T385 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1649191874 Jun 27 08:17:34 PM PDT 24 Jun 27 08:24:17 PM PDT 24 5298534198 ps
T693 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3261146994 Jun 27 08:28:32 PM PDT 24 Jun 27 08:33:55 PM PDT 24 2797943692 ps
T170 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.848288926 Jun 27 08:27:38 PM PDT 24 Jun 27 08:29:24 PM PDT 24 2629326010 ps
T387 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.100608410 Jun 27 08:48:01 PM PDT 24 Jun 27 08:54:01 PM PDT 24 3772720576 ps
T333 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2398774250 Jun 27 08:21:15 PM PDT 24 Jun 27 08:25:07 PM PDT 24 3074331018 ps
T120 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.578905270 Jun 27 08:28:53 PM PDT 24 Jun 27 08:42:36 PM PDT 24 3511752716 ps
T666 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.441597082 Jun 27 08:49:36 PM PDT 24 Jun 27 08:56:45 PM PDT 24 3533153660 ps
T671 /workspace/coverage/default/15.chip_sw_all_escalation_resets.1098677897 Jun 27 08:48:42 PM PDT 24 Jun 27 09:02:12 PM PDT 24 5985385352 ps
T30 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.498731739 Jun 27 08:26:14 PM PDT 24 Jun 27 08:37:36 PM PDT 24 3570336880 ps
T850 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1584238172 Jun 27 08:39:40 PM PDT 24 Jun 27 08:43:38 PM PDT 24 3084029569 ps
T851 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1656479800 Jun 27 08:35:32 PM PDT 24 Jun 27 08:55:35 PM PDT 24 5999690248 ps
T852 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3903392413 Jun 27 08:35:25 PM PDT 24 Jun 27 08:40:49 PM PDT 24 3439794648 ps
T58 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3307503687 Jun 27 08:19:52 PM PDT 24 Jun 27 08:34:27 PM PDT 24 8368338369 ps
T853 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3086583864 Jun 27 08:33:49 PM PDT 24 Jun 27 08:36:53 PM PDT 24 3391551160 ps
T150 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3590465220 Jun 27 08:17:26 PM PDT 24 Jun 27 08:30:38 PM PDT 24 4163929096 ps
T121 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2075860461 Jun 27 08:39:53 PM PDT 24 Jun 27 08:48:48 PM PDT 24 3779055544 ps
T651 /workspace/coverage/default/2.chip_sw_aes_masking_off.520576182 Jun 27 08:37:01 PM PDT 24 Jun 27 08:41:57 PM PDT 24 3069507619 ps
T266 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3293435085 Jun 27 08:27:48 PM PDT 24 Jun 27 08:40:08 PM PDT 24 6105254568 ps
T350 /workspace/coverage/default/74.chip_sw_all_escalation_resets.1634928438 Jun 27 08:56:00 PM PDT 24 Jun 27 09:05:06 PM PDT 24 4431721958 ps
T530 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2444152692 Jun 27 08:25:33 PM PDT 24 Jun 27 08:41:50 PM PDT 24 4910318440 ps
T228 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3069744802 Jun 27 08:37:08 PM PDT 24 Jun 27 08:45:05 PM PDT 24 3991032046 ps
T267 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.615571982 Jun 27 08:35:14 PM PDT 24 Jun 27 08:50:07 PM PDT 24 7358917500 ps
T72 /workspace/coverage/default/3.chip_tap_straps_prod.60783266 Jun 27 08:43:53 PM PDT 24 Jun 27 08:58:41 PM PDT 24 8687569839 ps
T723 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3915532364 Jun 27 08:53:03 PM PDT 24 Jun 27 09:01:02 PM PDT 24 4107629536 ps
T70 /workspace/coverage/default/2.chip_jtag_mem_access.3113354980 Jun 27 08:33:24 PM PDT 24 Jun 27 08:57:21 PM PDT 24 13292055312 ps
T308 /workspace/coverage/default/2.chip_plic_all_irqs_20.3246896221 Jun 27 08:39:07 PM PDT 24 Jun 27 08:52:27 PM PDT 24 4898539550 ps
T210 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.837396520 Jun 27 08:38:59 PM PDT 24 Jun 27 08:45:08 PM PDT 24 3289088406 ps
T367 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3199909715 Jun 27 08:45:25 PM PDT 24 Jun 27 08:50:57 PM PDT 24 3833878634 ps
T429 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.353604256 Jun 27 08:36:22 PM PDT 24 Jun 27 08:53:35 PM PDT 24 5648893262 ps
T52 /workspace/coverage/default/1.chip_sw_spi_device_tpm.1077627041 Jun 27 08:25:54 PM PDT 24 Jun 27 08:31:50 PM PDT 24 2777957170 ps
T163 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.597212097 Jun 27 08:51:32 PM PDT 24 Jun 27 08:58:26 PM PDT 24 4334255608 ps
T854 /workspace/coverage/default/2.chip_sw_example_flash.647084909 Jun 27 08:33:45 PM PDT 24 Jun 27 08:38:51 PM PDT 24 2517426504 ps
T390 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2674409551 Jun 27 08:35:02 PM PDT 24 Jun 27 08:57:39 PM PDT 24 6151436237 ps
T222 /workspace/coverage/default/3.chip_sw_uart_tx_rx.1131611363 Jun 27 08:43:47 PM PDT 24 Jun 27 08:53:53 PM PDT 24 4471327060 ps
T60 /workspace/coverage/default/0.chip_sw_alert_test.2433024613 Jun 27 08:19:07 PM PDT 24 Jun 27 08:25:13 PM PDT 24 2986847288 ps
T855 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3628718102 Jun 27 08:42:40 PM PDT 24 Jun 27 08:52:03 PM PDT 24 4714974536 ps
T33 /workspace/coverage/default/0.chip_sw_usbdev_stream.3137696829 Jun 27 08:18:41 PM PDT 24 Jun 27 09:34:54 PM PDT 24 18281408136 ps
T856 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3824740191 Jun 27 08:19:03 PM PDT 24 Jun 27 08:30:48 PM PDT 24 8196948452 ps
T287 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1853229135 Jun 27 08:26:05 PM PDT 24 Jun 27 08:36:44 PM PDT 24 4085995756 ps
T668 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2462550131 Jun 27 08:20:30 PM PDT 24 Jun 27 08:27:03 PM PDT 24 3551589150 ps
T227 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1571634301 Jun 27 08:27:29 PM PDT 24 Jun 27 08:34:27 PM PDT 24 5287943576 ps
T115 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.486916567 Jun 27 08:42:35 PM PDT 24 Jun 27 09:03:28 PM PDT 24 9634239734 ps
T673 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3773849109 Jun 27 08:48:10 PM PDT 24 Jun 27 08:55:48 PM PDT 24 3485760088 ps
T129 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1883195702 Jun 27 08:28:25 PM PDT 24 Jun 27 08:37:09 PM PDT 24 5098601074 ps
T122 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3400780913 Jun 27 08:30:28 PM PDT 24 Jun 27 08:42:45 PM PDT 24 5119201550 ps
T360 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3759655703 Jun 27 08:35:43 PM PDT 24 Jun 27 09:36:58 PM PDT 24 15787425473 ps
T223 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.696130441 Jun 27 08:49:33 PM PDT 24 Jun 27 08:57:54 PM PDT 24 4118172594 ps
T2 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.921825311 Jun 27 08:41:03 PM PDT 24 Jun 27 08:47:44 PM PDT 24 7036455128 ps
T73 /workspace/coverage/default/2.chip_tap_straps_dev.1125923201 Jun 27 08:40:06 PM PDT 24 Jun 27 09:03:47 PM PDT 24 14033153039 ps
T49 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.828282429 Jun 27 08:24:57 PM PDT 24 Jun 27 08:32:16 PM PDT 24 5992494800 ps
T361 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2435395080 Jun 27 08:26:03 PM PDT 24 Jun 27 09:39:16 PM PDT 24 15514857384 ps
T119 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2757750777 Jun 27 08:17:09 PM PDT 24 Jun 27 08:20:06 PM PDT 24 3792029063 ps
T343 /workspace/coverage/default/99.chip_sw_all_escalation_resets.1578036469 Jun 27 08:56:04 PM PDT 24 Jun 27 09:06:52 PM PDT 24 5324214642 ps
T176 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2694520793 Jun 27 08:26:17 PM PDT 24 Jun 27 08:33:55 PM PDT 24 4049448362 ps
T399 /workspace/coverage/default/0.chip_sw_csrng_smoketest.955447177 Jun 27 08:21:02 PM PDT 24 Jun 27 08:23:40 PM PDT 24 2345542876 ps
T400 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1570599878 Jun 27 08:55:37 PM PDT 24 Jun 27 09:02:15 PM PDT 24 3624316930 ps
T401 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.585855546 Jun 27 08:43:10 PM PDT 24 Jun 27 08:47:12 PM PDT 24 2217984760 ps
T177 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3767241838 Jun 27 08:20:03 PM PDT 24 Jun 27 08:27:23 PM PDT 24 4164880487 ps
T323 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2008864463 Jun 27 08:16:36 PM PDT 24 Jun 27 08:30:03 PM PDT 24 4185441770 ps
T654 /workspace/coverage/default/29.chip_sw_all_escalation_resets.2330946000 Jun 27 08:54:36 PM PDT 24 Jun 27 09:03:52 PM PDT 24 5405382392 ps
T857 /workspace/coverage/default/2.rom_keymgr_functest.516757889 Jun 27 08:43:19 PM PDT 24 Jun 27 08:53:08 PM PDT 24 5130130068 ps
T53 /workspace/coverage/default/2.chip_sw_spi_device_tpm.1481611069 Jun 27 08:33:43 PM PDT 24 Jun 27 08:40:36 PM PDT 24 3423612765 ps
T153 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2200733247 Jun 27 08:24:02 PM PDT 24 Jun 27 08:49:59 PM PDT 24 9857209320 ps
T858 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3153813502 Jun 27 08:29:28 PM PDT 24 Jun 27 08:38:46 PM PDT 24 5527110000 ps
T265 /workspace/coverage/default/84.chip_sw_all_escalation_resets.4004736644 Jun 27 08:54:05 PM PDT 24 Jun 27 09:04:08 PM PDT 24 5860950868 ps
T859 /workspace/coverage/default/2.chip_sw_aes_idle.3522129115 Jun 27 08:37:43 PM PDT 24 Jun 27 08:41:48 PM PDT 24 2160930140 ps
T126 /workspace/coverage/default/0.chip_sw_edn_boot_mode.4031866993 Jun 27 08:21:03 PM PDT 24 Jun 27 08:31:13 PM PDT 24 2846568924 ps
T650 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3209114379 Jun 27 08:57:11 PM PDT 24 Jun 27 09:55:56 PM PDT 24 11627099032 ps
T268 /workspace/coverage/default/77.chip_sw_all_escalation_resets.61143361 Jun 27 08:53:16 PM PDT 24 Jun 27 09:04:23 PM PDT 24 6144186776 ps
T652 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3983117950 Jun 27 08:56:16 PM PDT 24 Jun 27 09:03:12 PM PDT 24 4334487932 ps
T669 /workspace/coverage/default/21.chip_sw_all_escalation_resets.1035549361 Jun 27 08:50:54 PM PDT 24 Jun 27 09:01:24 PM PDT 24 4865571640 ps
T79 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1981767775 Jun 27 08:19:48 PM PDT 24 Jun 27 08:26:10 PM PDT 24 4973290888 ps
T860 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2655752154 Jun 27 08:26:03 PM PDT 24 Jun 27 09:36:57 PM PDT 24 15152086980 ps
T334 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.777257629 Jun 27 08:31:51 PM PDT 24 Jun 27 08:36:52 PM PDT 24 2625812416 ps
T347 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1975314732 Jun 27 08:22:56 PM PDT 24 Jun 27 08:26:04 PM PDT 24 3153461880 ps
T368 /workspace/coverage/default/6.chip_sw_all_escalation_resets.3253592020 Jun 27 08:57:21 PM PDT 24 Jun 27 09:08:09 PM PDT 24 4748857720 ps
T257 /workspace/coverage/default/0.chip_sw_plic_sw_irq.2652803076 Jun 27 08:19:26 PM PDT 24 Jun 27 08:23:14 PM PDT 24 2977246184 ps
T861 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1389248348 Jun 27 08:36:36 PM PDT 24 Jun 27 08:50:41 PM PDT 24 6203917492 ps
T862 /workspace/coverage/default/1.chip_sw_example_manufacturer.127463379 Jun 27 08:22:19 PM PDT 24 Jun 27 08:25:13 PM PDT 24 2493314170 ps
T430 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1050138929 Jun 27 08:38:33 PM PDT 24 Jun 27 08:56:23 PM PDT 24 6873191011 ps
T340 /workspace/coverage/default/3.chip_sw_all_escalation_resets.2627408211 Jun 27 08:43:32 PM PDT 24 Jun 27 08:58:41 PM PDT 24 5066875628 ps
T171 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3017315728 Jun 27 08:37:39 PM PDT 24 Jun 27 10:03:08 PM PDT 24 48750914370 ps
T322 /workspace/coverage/default/1.chip_sw_otbn_randomness.1821619325 Jun 27 08:35:01 PM PDT 24 Jun 27 08:53:26 PM PDT 24 6044455624 ps
T863 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3827617423 Jun 27 08:18:33 PM PDT 24 Jun 27 08:26:36 PM PDT 24 5757959024 ps
T74 /workspace/coverage/default/0.chip_sw_usbdev_pullup.3619555000 Jun 27 08:16:56 PM PDT 24 Jun 27 08:23:15 PM PDT 24 3303290440 ps
T864 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3971019083 Jun 27 08:25:07 PM PDT 24 Jun 27 09:32:28 PM PDT 24 40537850972 ps
T670 /workspace/coverage/default/90.chip_sw_all_escalation_resets.3002635026 Jun 27 08:55:27 PM PDT 24 Jun 27 09:04:19 PM PDT 24 4378033028 ps
T865 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.59802842 Jun 27 08:39:49 PM PDT 24 Jun 27 08:50:05 PM PDT 24 4186733948 ps
T866 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3088976808 Jun 27 08:37:56 PM PDT 24 Jun 27 09:26:41 PM PDT 24 11917846260 ps
T258 /workspace/coverage/default/2.chip_sw_plic_sw_irq.2706119570 Jun 27 08:39:50 PM PDT 24 Jun 27 08:44:54 PM PDT 24 2884536740 ps
T71 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3474417548 Jun 27 08:30:50 PM PDT 24 Jun 27 08:44:33 PM PDT 24 6015829760 ps
T151 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1153506782 Jun 27 08:44:04 PM PDT 24 Jun 27 08:53:18 PM PDT 24 4437927672 ps
T3 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2128215905 Jun 27 08:20:21 PM PDT 24 Jun 27 08:28:19 PM PDT 24 7616235300 ps
T288 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2811358432 Jun 27 08:30:25 PM PDT 24 Jun 27 08:42:23 PM PDT 24 5407410184 ps
T186 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.141133728 Jun 27 08:21:41 PM PDT 24 Jun 27 08:37:13 PM PDT 24 9793487984 ps
T867 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1780819823 Jun 27 08:22:22 PM PDT 24 Jun 27 08:31:25 PM PDT 24 3678826610 ps
T393 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3522416424 Jun 27 08:24:38 PM PDT 24 Jun 27 08:29:33 PM PDT 24 3024722632 ps
T83 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2260973210 Jun 27 08:26:33 PM PDT 24 Jun 27 08:46:26 PM PDT 24 10984065896 ps
T868 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3252873073 Jun 27 08:19:38 PM PDT 24 Jun 27 08:23:22 PM PDT 24 3142821404 ps
T869 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1860868199 Jun 27 08:33:17 PM PDT 24 Jun 27 08:38:20 PM PDT 24 3184699600 ps
T211 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2571663892 Jun 27 08:18:08 PM PDT 24 Jun 27 08:28:57 PM PDT 24 4545487770 ps
T870 /workspace/coverage/default/2.chip_sw_kmac_idle.207733631 Jun 27 08:40:27 PM PDT 24 Jun 27 08:43:41 PM PDT 24 2327189334 ps
T216 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1169824885 Jun 27 08:37:34 PM PDT 24 Jun 27 09:11:14 PM PDT 24 7593981648 ps
T253 /workspace/coverage/default/23.chip_sw_all_escalation_resets.368730189 Jun 27 08:49:02 PM PDT 24 Jun 27 09:02:28 PM PDT 24 5571888660 ps
T295 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3776047325 Jun 27 08:29:50 PM PDT 24 Jun 27 08:43:15 PM PDT 24 5189553472 ps
T296 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.571930229 Jun 27 08:23:10 PM PDT 24 Jun 27 08:35:39 PM PDT 24 4021085230 ps
T172 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3763659917 Jun 27 08:17:43 PM PDT 24 Jun 27 08:39:00 PM PDT 24 10487249784 ps
T179 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1538540888 Jun 27 08:17:30 PM PDT 24 Jun 27 08:19:52 PM PDT 24 2779469163 ps
T297 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.775184008 Jun 27 08:23:58 PM PDT 24 Jun 27 08:35:48 PM PDT 24 9660626772 ps
T298 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.346373583 Jun 27 08:45:33 PM PDT 24 Jun 27 08:58:24 PM PDT 24 9612113099 ps
T31 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1389342407 Jun 27 08:17:56 PM PDT 24 Jun 27 08:27:52 PM PDT 24 4863016002 ps
T299 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1069357371 Jun 27 08:27:31 PM PDT 24 Jun 27 08:32:36 PM PDT 24 2516024762 ps
T154 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3158142246 Jun 27 08:18:12 PM PDT 24 Jun 27 09:17:08 PM PDT 24 17712161096 ps
T431 /workspace/coverage/default/1.chip_sw_kmac_entropy.2701247175 Jun 27 08:24:09 PM PDT 24 Jun 27 08:28:51 PM PDT 24 2626104724 ps
T63 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.4078078951 Jun 27 08:17:48 PM PDT 24 Jun 27 08:27:40 PM PDT 24 3117855672 ps
T386 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1019554654 Jun 27 08:38:26 PM PDT 24 Jun 27 08:43:39 PM PDT 24 2773793330 ps
T309 /workspace/coverage/default/1.chip_plic_all_irqs_20.700280233 Jun 27 08:31:10 PM PDT 24 Jun 27 08:39:02 PM PDT 24 4764259800 ps
T415 /workspace/coverage/default/39.chip_sw_all_escalation_resets.479494011 Jun 27 08:49:57 PM PDT 24 Jun 27 08:59:46 PM PDT 24 6200195214 ps
T418 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2448028059 Jun 27 08:19:04 PM PDT 24 Jun 27 08:36:26 PM PDT 24 5282692786 ps
T362 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3928498133 Jun 27 08:27:34 PM PDT 24 Jun 27 10:09:31 PM PDT 24 23968269360 ps
T127 /workspace/coverage/default/2.chip_sw_edn_kat.1898438892 Jun 27 08:39:31 PM PDT 24 Jun 27 08:51:27 PM PDT 24 3246763140 ps
T419 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1328372302 Jun 27 08:28:32 PM PDT 24 Jun 27 09:08:13 PM PDT 24 24983587454 ps
T420 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3091432631 Jun 27 08:50:54 PM PDT 24 Jun 27 09:12:40 PM PDT 24 5434395360 ps
T313 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1783672035 Jun 27 08:34:41 PM PDT 24 Jun 27 08:49:08 PM PDT 24 5345265220 ps
T421 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3732898021 Jun 27 08:18:36 PM PDT 24 Jun 27 08:29:41 PM PDT 24 4731873560 ps
T422 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1770403949 Jun 27 08:38:15 PM PDT 24 Jun 27 08:44:10 PM PDT 24 2803706544 ps
T109 /workspace/coverage/default/0.chip_sw_power_sleep_load.1468742875 Jun 27 08:18:54 PM PDT 24 Jun 27 08:27:01 PM PDT 24 4177427702 ps
T84 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.4094269987 Jun 27 08:36:43 PM PDT 24 Jun 27 08:42:06 PM PDT 24 3229120311 ps
T231 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2713432745 Jun 27 08:47:00 PM PDT 24 Jun 27 08:53:42 PM PDT 24 3689179158 ps
T193 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1271583577 Jun 27 08:38:09 PM PDT 24 Jun 27 08:52:13 PM PDT 24 7782017176 ps
T363 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.489992301 Jun 27 08:22:13 PM PDT 24 Jun 27 09:19:36 PM PDT 24 15437082110 ps
T871 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1723869431 Jun 27 08:22:12 PM PDT 24 Jun 27 08:28:03 PM PDT 24 4942828012 ps
T357 /workspace/coverage/default/91.chip_sw_all_escalation_resets.742484715 Jun 27 08:55:04 PM PDT 24 Jun 27 09:05:05 PM PDT 24 5347712124 ps
T377 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1215470137 Jun 27 08:53:00 PM PDT 24 Jun 27 08:59:15 PM PDT 24 2999299998 ps
T378 /workspace/coverage/default/2.chip_sw_hmac_smoketest.453490672 Jun 27 08:42:29 PM PDT 24 Jun 27 08:47:09 PM PDT 24 2895504124 ps
T379 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3271047224 Jun 27 08:26:39 PM PDT 24 Jun 27 08:31:24 PM PDT 24 3273527262 ps
T80 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.246383960 Jun 27 08:23:56 PM PDT 24 Jun 27 09:06:45 PM PDT 24 24797751934 ps
T380 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2821145567 Jun 27 08:36:33 PM PDT 24 Jun 27 08:46:53 PM PDT 24 7848777564 ps
T187 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3164847629 Jun 27 08:32:29 PM PDT 24 Jun 27 08:38:19 PM PDT 24 3104084548 ps
T85 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2733313939 Jun 27 08:26:32 PM PDT 24 Jun 27 08:32:38 PM PDT 24 2919835679 ps
T381 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2361434035 Jun 27 08:31:53 PM PDT 24 Jun 27 08:35:53 PM PDT 24 3166682728 ps
T8 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1087816172 Jun 27 08:30:11 PM PDT 24 Jun 27 08:36:09 PM PDT 24 4079291912 ps
T872 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3409309325 Jun 27 08:26:47 PM PDT 24 Jun 27 08:30:31 PM PDT 24 3513650725 ps
T434 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1503045468 Jun 27 08:36:32 PM PDT 24 Jun 27 09:41:14 PM PDT 24 19307381147 ps
T718 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.922013390 Jun 27 08:49:13 PM PDT 24 Jun 27 08:55:29 PM PDT 24 4193820620 ps
T352 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1600822110 Jun 27 08:36:12 PM PDT 24 Jun 27 08:43:04 PM PDT 24 4212181824 ps
T873 /workspace/coverage/default/1.chip_sw_aes_entropy.3150914646 Jun 27 08:27:21 PM PDT 24 Jun 27 08:31:19 PM PDT 24 2439254456 ps
T874 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.176394049 Jun 27 08:18:50 PM PDT 24 Jun 27 08:25:06 PM PDT 24 4732878676 ps
T358 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1825209904 Jun 27 08:50:20 PM PDT 24 Jun 27 09:00:05 PM PDT 24 3138425320 ps
T875 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.276573729 Jun 27 08:41:58 PM PDT 24 Jun 27 08:45:41 PM PDT 24 2885768688 ps
T416 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2962039704 Jun 27 08:56:10 PM PDT 24 Jun 27 09:02:34 PM PDT 24 3475214040 ps
T876 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.415693411 Jun 27 08:21:41 PM PDT 24 Jun 27 08:30:24 PM PDT 24 5139699186 ps
T371 /workspace/coverage/default/1.chip_sw_edn_boot_mode.3035698377 Jun 27 08:30:32 PM PDT 24 Jun 27 08:40:09 PM PDT 24 3291876490 ps
T649 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4075180921 Jun 27 08:42:11 PM PDT 24 Jun 27 09:44:05 PM PDT 24 25134016505 ps
T66 /workspace/coverage/default/1.chip_tap_straps_rma.3107390602 Jun 27 08:32:02 PM PDT 24 Jun 27 08:48:49 PM PDT 24 9301408223 ps
T325 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3887511927 Jun 27 08:33:31 PM PDT 24 Jun 27 08:52:49 PM PDT 24 8471423209 ps
T67 /workspace/coverage/default/4.chip_tap_straps_rma.511779571 Jun 27 08:56:29 PM PDT 24 Jun 27 09:03:39 PM PDT 24 5903487245 ps
T164 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2690660921 Jun 27 08:38:00 PM PDT 24 Jun 27 09:03:26 PM PDT 24 11811888888 ps
T364 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.783094177 Jun 27 08:20:00 PM PDT 24 Jun 27 08:27:06 PM PDT 24 5572278444 ps
T877 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.739862123 Jun 27 08:27:51 PM PDT 24 Jun 27 08:38:39 PM PDT 24 6700118340 ps
T655 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.609786603 Jun 27 08:26:00 PM PDT 24 Jun 27 09:39:51 PM PDT 24 14987629150 ps
T878 /workspace/coverage/default/2.chip_sw_uart_smoketest.4252780143 Jun 27 08:44:05 PM PDT 24 Jun 27 08:49:53 PM PDT 24 3291663108 ps
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