Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	453	1			T534	1		T591	7		T542	1
all_values[1]	444	1			T423	1		T543	2		T591	2
all_values[2]	442	1			T423	1		T435	1		T591	3
all_values[3]	452	1			T591	1		T453	3		T439	4
all_values[4]	434	1			T539	1		T591	1		T542	1
all_values[5]	438	1			T591	3		T453	4		T439	5
all_values[6]	468	1			T675	1		T534	1		T591	1
all_values[7]	470	1			T423	1		T591	2		T453	2
all_values[8]	509	1			T675	1		T591	2		T542	1
all_values[9]	460	1			T423	1		T534	1		T539	1
all_values[10]	460	1			T423	1		T591	1		T542	1
all_values[11]	481	1			T423	2		T675	1		T534	1
all_values[12]	496	1			T82	2		T423	1		T534	2
all_values[13]	484	1			T534	1		T591	4		T453	4
all_values[14]	489	1			T534	1		T539	1		T543	1
all_values[15]	473	1			T591	5		T453	1		T439	2
all_values[16]	490	1			T539	1		T591	4		T453	7
all_values[17]	457	1			T423	1		T591	2		T453	8
all_values[18]	434	1			T423	1		T534	1		T591	4
all_values[19]	479	1			T423	2		T543	1		T542	1
all_values[20]	452	1			T82	1		T675	1		T539	3
all_values[21]	472	1			T82	1		T423	2		T534	1
all_values[22]	426	1			T82	2		T423	1		T591	3
all_values[23]	460	1			T539	1		T591	2		T453	4
all_values[24]	470	1			T423	1		T534	1		T543	1
all_values[25]	459	1			T534	1		T542	1		T453	4
all_values[26]	440	1			T82	1		T675	1		T539	1
all_values[27]	507	1			T82	1		T423	1		T534	1
all_values[28]	467	1			T82	1		T591	2		T453	2
all_values[29]	454	1			T675	1		T591	4		T453	5
all_values[30]	464	1			T423	1		T591	2		T536	2
all_values[31]	453	1			T591	1		T542	1		T453	1
all_values[32]	442	1			T423	1		T453	2		T439	4
all_values[33]	488	1			T82	1		T539	1		T543	1
all_values[34]	470	1			T82	2		T423	2		T675	1
all_values[35]	458	1			T543	1		T591	4		T536	2
all_values[36]	508	1			T423	1		T591	4		T453	3
all_values[37]	476	1			T82	1		T423	2		T534	1
all_values[38]	469	1			T82	1		T423	1		T591	2
all_values[39]	426	1			T591	2		T453	3		T439	3
all_values[40]	467	1			T82	1		T591	6		T536	1
all_values[41]	486	1			T82	1		T423	1		T591	3
all_values[42]	483	1			T423	1		T539	1		T591	4
all_values[43]	461	1			T82	1		T435	1		T534	1
all_values[44]	466	1			T82	1		T591	3		T453	1
all_values[45]	464	1			T423	1		T534	2		T539	1
all_values[46]	456	1			T423	1		T543	1		T591	3
all_values[47]	501	1			T453	4		T439	1		T576	4
all_values[48]	471	1			T423	1		T435	1		T591	4
all_values[49]	432	1			T591	3		T542	1		T536	1