Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3400	1			T423	2		T435	2		T591	7
all_values[1]	3304	1			T423	3		T435	2		T591	13
all_values[2]	3449	1			T435	5		T591	26		T542	1
all_values[3]	3383	1			T423	1		T435	3		T591	13
all_values[4]	3443	1			T435	1		T591	9		T542	2
all_values[5]	3455	1			T423	2		T435	2		T591	18
all_values[6]	3324	1			T423	2		T591	17		T453	27
all_values[7]	3420	1			T591	17		T542	1		T453	27
all_values[8]	3537	1			T423	1		T435	2		T591	17
all_values[9]	3545	1			T435	2		T591	12		T542	2
all_values[10]	3520	1			T423	1		T435	3		T591	9
all_values[11]	3382	1			T591	9		T542	1		T453	23
all_values[12]	3400	1			T423	2		T435	1		T591	14
all_values[13]	3432	1			T435	1		T591	17		T542	1
all_values[14]	3365	1			T423	2		T435	2		T591	13
all_values[15]	3454	1			T435	1		T591	15		T453	30
all_values[16]	3465	1			T423	1		T435	2		T591	14
all_values[17]	3453	1			T591	20		T453	32		T620	1
all_values[18]	3505	1			T423	2		T435	4		T591	20
all_values[19]	3527	1			T423	1		T591	14		T542	1
all_values[20]	3434	1			T423	1		T435	3		T591	10
all_values[21]	3568	1			T423	3		T435	3		T591	11
all_values[22]	3570	1			T423	1		T435	4		T591	22
all_values[23]	3408	1			T435	1		T591	12		T453	24
all_values[24]	3492	1			T423	1		T435	3		T591	18
all_values[25]	3480	1			T423	1		T435	1		T591	10
all_values[26]	3488	1			T423	2		T435	3		T591	11
all_values[27]	3435	1			T435	1		T591	19		T453	24
all_values[28]	3481	1			T435	1		T591	6		T542	1
all_values[29]	3538	1			T423	1		T435	5		T591	17
all_values[30]	3445	1			T435	4		T591	19		T542	2
all_values[31]	3476	1			T423	1		T435	2		T591	16
all_values[32]	3469	1			T423	4		T435	4		T591	9
all_values[33]	3439	1			T591	12		T453	20		T439	23
all_values[34]	3484	1			T423	1		T435	2		T591	16
all_values[35]	3484	1			T423	1		T435	1		T591	12
all_values[36]	3511	1			T423	2		T435	1		T591	17
all_values[37]	3392	1			T435	1		T591	14		T542	6
all_values[38]	3412	1			T591	17		T542	3		T453	24
all_values[39]	3471	1			T435	2		T591	12		T453	23
all_values[40]	3452	1			T423	1		T435	1		T591	16
all_values[41]	3442	1			T423	1		T435	3		T591	16
all_values[42]	3378	1			T423	2		T435	1		T591	10
all_values[43]	3426	1			T423	1		T435	4		T591	11
all_values[44]	3420	1			T423	2		T435	2		T591	13
all_values[45]	3521	1			T423	1		T435	5		T591	15
all_values[46]	3523	1			T423	1		T435	2		T591	17
all_values[47]	3402	1			T435	2		T591	9		T542	5
all_values[48]	3438	1			T435	5		T591	12		T542	2
all_values[49]	3487	1			T435	3		T591	18		T542	3
all_values[50]	3463	1			T435	1		T591	11		T453	27
all_values[51]	3486	1			T435	4		T591	20		T542	1
all_values[52]	3479	1			T423	1		T435	2		T591	16
all_values[53]	3415	1			T423	2		T435	3		T591	15
all_values[54]	3562	1			T423	1		T435	2		T591	17
all_values[55]	3464	1			T423	1		T435	2		T591	19
all_values[56]	3410	1			T423	1		T435	3		T591	20
all_values[57]	3424	1			T423	2		T435	2		T591	9
all_values[58]	3426	1			T435	1		T591	18		T542	2
all_values[59]	3494	1			T435	2		T591	16		T542	3
all_values[60]	3359	1			T423	3		T435	1		T591	15
all_values[61]	3517	1			T435	3		T591	9		T542	2
all_values[62]	3359	1			T423	1		T435	1		T591	10
all_values[63]	3552	1			T423	2		T435	5		T591	19