Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	172957	1			T72	158		T73	3		T74	4
values[2]	4835	1			T491	5		T524	2		T498	1
values[3]	2320	1			T537	1		T532	1		T598	1
values[4]	1627	1			T537	1		T532	1		T781	1
values[5]	1360	1			T537	1		T532	1		T781	1
values[6]	1207	1			T537	1		T532	1		T781	1
values[7]	1036	1			T537	1		T532	1		T781	1
values[8]	952	1			T537	1		T532	1		T781	1
values[9]	785	1			T537	1		T532	1		T781	1
values[10]	683	1			T537	1		T532	1		T781	1
values[11]	583	1			T537	1		T532	1		T781	1
values[12]	514	1			T537	1		T532	1		T781	1
values[13]	450	1			T537	1		T532	1		T781	1
values[14]	398	1			T537	1		T532	1		T781	1
values[15]	361	1			T537	1		T532	1		T781	1
values[16]	360	1			T537	1		T532	1		T781	1
values[17]	386	1			T537	1		T532	1		T781	1
values[18]	411	1			T537	1		T532	1		T781	1
values[19]	390	1			T537	1		T532	1		T781	1
values[20]	395	1			T537	1		T532	1		T781	1
values[21]	378	1			T537	1		T532	1		T781	1
values[22]	451	1			T537	1		T532	1		T781	1
values[23]	455	1			T537	1		T532	1		T781	1
values[24]	440	1			T537	1		T532	1		T781	1
values[25]	365	1			T537	1		T532	1		T781	1
values[26]	297	1			T537	1		T532	1		T781	1
values[27]	273	1			T537	1		T532	1		T781	1
values[28]	217	1			T537	1		T532	1		T781	1
values[29]	171	1			T537	1		T532	1		T781	1
values[30]	141	1			T537	1		T532	1		T781	1
values[31]	113	1			T537	1		T532	1		T781	1
values[32]	107	1			T537	1		T532	1		T781	1
values[33]	163	1			T537	1		T532	1		T781	1
values[34]	143	1			T537	1		T532	1		T781	1
values[35]	119	1			T537	1		T532	1		T781	1
values[36]	130	1			T537	1		T532	1		T781	1
values[37]	141	1			T537	1		T532	1		T781	1
values[38]	124	1			T537	1		T532	1		T781	1
values[39]	128	1			T537	1		T532	1		T781	1
values[40]	157	1			T537	1		T532	1		T781	1
values[41]	127	1			T537	1		T532	1		T781	1
values[42]	103	1			T537	1		T532	1		T781	1
values[43]	93	1			T537	1		T532	1		T781	1
values[44]	85	1			T537	1		T532	1		T781	1
values[45]	78	1			T537	1		T532	1		T781	1
values[46]	75	1			T537	1		T532	1		T781	1
values[47]	72	1			T537	1		T532	1		T781	1
values[48]	72	1			T537	1		T532	1		T781	1
values[49]	79	1			T537	1		T532	1		T781	1
values[50]	78	1			T537	1		T532	1		T781	1
values[51]	75	1			T537	1		T532	1		T781	1
values[52]	92	1			T537	1		T532	1		T781	1
values[53]	83	1			T537	1		T532	1		T781	1
values[54]	76	1			T537	1		T532	1		T781	1
values[55]	79	1			T537	1		T532	1		T781	1
values[56]	68	1			T537	1		T532	1		T781	1
values[57]	64	1			T537	1		T532	1		T781	1
values[58]	68	1			T537	1		T532	1		T781	1
values[59]	50	1			T537	1		T532	1		T781	1
values[60]	65	1			T537	1		T532	1		T781	1
values[61]	62	1			T537	1		T532	1		T781	1
values[62]	55	1			T537	1		T532	1		T781	1
values[63]	60	1			T537	1		T532	1		T781	1
values[64]	69	1			T537	1		T532	1		T781	1
values[65]	77	1			T537	1		T532	1		T781	1
values[66]	51	1			T537	1		T532	1		T781	1
values[67]	67	1			T537	1		T532	1		T781	1
values[68]	72	1			T537	1		T532	1		T781	1
values[69]	59	1			T537	1		T532	1		T781	1
values[70]	55	1			T537	1		T532	1		T781	1
values[71]	52	1			T537	1		T532	1		T781	1
values[72]	58	1			T537	1		T532	1		T781	1
values[73]	60	1			T537	1		T532	3		T781	1
values[74]	75	1			T537	1		T532	10		T781	1
values[75]	80	1			T537	1		T532	13		T781	1
values[76]	72	1			T537	1		T532	7		T781	1
values[77]	75	1			T537	1		T532	6		T781	1
values[78]	81	1			T537	1		T532	2		T781	1
values[79]	80	1			T537	1		T532	4		T781	1
values[80]	78	1			T537	1		T532	5		T781	1
values[81]	84	1			T537	1		T532	3		T781	1
values[82]	102	1			T537	1		T532	4		T781	1
values[83]	83	1			T537	1		T532	3		T781	1
values[84]	103	1			T537	1		T532	6		T781	2
values[85]	102	1			T537	1		T532	3		T781	3
values[86]	86	1			T537	1		T532	2		T781	4
values[87]	91	1			T537	1		T532	2		T781	2
values[88]	84	1			T537	1		T532	4		T781	4
values[89]	110	1			T537	1		T532	4		T781	5
values[90]	98	1			T537	1		T532	3		T781	7
values[91]	99	1			T537	1		T532	1		T781	1
values[92]	78	1			T537	1		T532	3		T781	1
values[93]	110	1			T537	1		T532	4		T781	2
values[94]	106	1			T537	1		T532	1		T781	4
values[95]	93	1			T537	1		T532	3		T781	2
values[96]	97	1			T537	1		T532	1		T781	1
values[97]	82	1			T537	1		T532	1		T781	2
values[98]	83	1			T537	1		T532	1		T781	1
values[99]	81	1			T537	1		T532	1		T781	10
values[100]	94	1			T537	1		T532	1		T781	6
values[101]	75	1			T537	1		T532	1		T781	1
values[102]	97	1			T537	2		T532	1		T781	3
values[103]	97	1			T537	1		T532	2		T781	6
values[104]	88	1			T537	1		T532	1		T781	1
values[105]	91	1			T537	1		T532	3		T781	1
values[106]	100	1			T537	1		T532	6		T781	3
values[107]	92	1			T537	1		T532	3		T781	3
values[108]	104	1			T537	1		T532	1		T781	2
values[109]	104	1			T537	1		T532	1		T781	4
values[110]	120	1			T537	1		T532	1		T781	1
values[111]	124	1			T537	1		T532	3		T781	2
values[112]	90	1			T537	1		T532	2		T781	2
values[113]	102	1			T537	1		T532	3		T781	1
values[114]	115	1			T537	1		T532	8		T781	5
values[115]	114	1			T537	1		T532	3		T781	4
values[116]	122	1			T537	1		T532	5		T781	1
values[117]	113	1			T537	1		T532	1		T781	1
values[118]	111	1			T537	1		T532	1		T781	1
values[119]	116	1			T537	1		T532	7		T781	2
values[120]	121	1			T537	1		T532	3		T781	7
values[121]	123	1			T537	2		T532	1		T781	4
values[122]	141	1			T537	3		T532	1		T781	1
values[123]	170	1			T537	6		T532	3		T781	4
values[124]	247	1			T537	2		T532	1		T781	1
values[125]	526	1			T537	3		T532	1		T781	1
values[126]	949	1			T537	31		T532	14		T781	28
values[127]	2715	1			T537	156		T532	106		T781	114
values[128]	4308	1			T537	216		T532	150		T781	175