Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.15	95.47	94.09	95.20		94.91	97.71	99.54

Total tests in report: 2885

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.61	39.61	44.91	44.91	43.09	43.09	31.69	31.69			57.99	57.99	59.62	59.62	0.39	0.39	/workspace/coverage/default/40.chip_sw_all_escalation_resets.4002988025
49.45	9.83	52.82	7.91	51.99	8.90	39.16	7.47			65.76	7.77	85.84	26.22	1.12	0.73	/workspace/coverage/default/0.chip_jtag_csr_rw.3541268598
55.19	5.74	65.27	12.45	60.31	8.31	41.46	2.30			77.14	11.38	85.84	0.00	1.12	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2233226304
59.85	4.66	75.30	10.03	63.41	3.10	47.04	5.57			77.47	0.32	85.84	0.00	10.03	8.92	/workspace/coverage/cover_reg_top/95.xbar_stress_all.99193960
64.22	4.37	75.30	0.00	63.41	0.00	47.04	0.00			77.47	0.00	85.84	0.00	36.24	26.20	/workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.765417749
67.67	3.45	81.22	5.92	67.73	4.32	50.96	3.93			79.48	2.01	90.38	4.55	36.24	0.00	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3975077905
70.81	3.14	81.29	0.07	69.28	1.55	50.96	0.00			79.79	0.31	90.38	0.00	53.17	16.93	/workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.949683552
73.40	2.59	81.30	0.01	69.30	0.02	66.39	15.43			79.81	0.02	90.38	0.00	53.21	0.05	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3815675801
75.86	2.46	83.99	2.69	75.53	6.22	66.54	0.15			84.90	5.10	90.38	0.00	53.81	0.60	/workspace/coverage/cover_reg_top/4.chip_csr_rw.20175261
78.00	2.14	86.57	2.58	78.52	3.00	70.92	4.38			87.25	2.34	90.91	0.52	53.81	0.00	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.761080570
79.65	1.65	86.57	0.00	78.65	0.13	70.92	0.00			87.26	0.02	90.91	0.00	63.59	9.78	/workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2074183521
81.00	1.35	86.57	0.00	78.88	0.23	70.92	0.00			87.26	0.00	90.91	0.00	71.47	7.88	/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3779107350
82.27	1.27	86.73	0.17	78.98	0.10	77.92	7.00			87.44	0.18	91.08	0.17	71.47	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3267113822
83.46	1.19	88.66	1.93	81.12	2.14	79.10	1.18			89.35	1.91	91.08	0.00	71.47	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2301892530
84.65	1.18	88.66	0.00	81.12	0.00	79.10	0.00			89.35	0.00	91.08	0.00	78.58	7.11	/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.4024885681
85.54	0.89	88.66	0.00	81.24	0.12	79.10	0.00			89.35	0.00	91.08	0.00	83.81	5.23	/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2906961315
86.34	0.80	89.91	1.25	82.26	1.03	80.40	1.30			90.55	1.19	91.08	0.00	83.81	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.4167187838
87.07	0.74	90.23	0.32	82.38	0.11	80.42	0.01			90.67	0.12	94.93	3.85	83.81	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1641065444
87.71	0.64	90.90	0.67	82.96	0.58	81.77	1.35			91.35	0.68	95.45	0.52	83.86	0.05	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3677851898
88.35	0.63	90.90	0.01	83.07	0.11	82.55	0.78			91.38	0.03	95.45	0.00	86.73	2.88	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.716457461
88.97	0.62	91.61	0.71	84.19	1.12	83.45	0.90			92.37	0.98	95.45	0.00	86.73	0.00	/workspace/coverage/default/1.chip_sw_gpio.633080103
89.51	0.54	91.62	0.01	87.01	2.83	83.45	0.00			92.37	0.00	95.45	0.00	87.15	0.41	/workspace/coverage/cover_reg_top/6.chip_tl_errors.3219242488
90.03	0.52	91.62	0.00	87.07	0.06	83.45	0.00			92.37	0.00	95.45	0.00	90.21	3.07	/workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.1178779485
90.46	0.44	91.77	0.15	87.25	0.18	85.46	2.01			92.49	0.13	95.45	0.00	90.35	0.14	/workspace/coverage/default/2.chip_jtag_csr_rw.2828157847
90.90	0.43	92.52	0.75	88.01	0.77	85.98	0.51			93.01	0.52	95.45	0.00	90.41	0.06	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3718709422
91.29	0.39	92.52	0.00	88.09	0.07	85.98	0.00			93.01	0.00	95.45	0.00	92.67	2.26	/workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2318706377
91.67	0.38	93.01	0.50	89.65	1.56	86.01	0.03			93.14	0.12	95.45	0.00	92.76	0.09	/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.365354823
92.01	0.34	93.02	0.01	89.65	0.01	88.01	2.00			93.14	0.00	95.45	0.00	92.81	0.05	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.977952737
92.34	0.33	93.02	0.00	89.65	0.00	89.04	1.02			93.14	0.00	95.45	0.00	93.74	0.93	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1778233307
92.59	0.25	93.52	0.50	90.09	0.44	89.17	0.14			93.55	0.41	95.45	0.00	93.74	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.496472061
92.83	0.24	93.52	0.00	90.16	0.07	89.17	0.00			93.55	0.00	95.45	0.00	95.12	1.39	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.269158479
93.06	0.23	93.58	0.06	90.18	0.01	89.79	0.61			93.56	0.01	96.15	0.70	95.14	0.01	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.188756077
93.25	0.19	93.58	0.00	90.42	0.25	89.79	0.00			93.59	0.03	96.15	0.00	95.97	0.83	/workspace/coverage/cover_reg_top/72.xbar_stress_all.2359783142
93.40	0.15	93.58	0.00	90.42	0.00	90.71	0.93			93.59	0.00	96.15	0.00	95.97	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1819739911
93.56	0.15	93.77	0.20	90.57	0.14	90.82	0.11			93.71	0.12	96.50	0.35	95.97	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1647424547
93.70	0.15	93.98	0.21	90.89	0.32	91.17	0.35			93.71	0.00	96.50	0.00	95.97	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1880395165
93.84	0.13	94.02	0.03	90.93	0.04	91.66	0.49			93.72	0.01	96.50	0.00	96.18	0.21	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3788223067
93.96	0.12	94.05	0.04	91.25	0.32	91.69	0.04			94.08	0.36	96.50	0.00	96.18	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4170653254
94.08	0.12	94.05	0.00	91.26	0.01	91.69	0.00			94.08	0.00	96.50	0.00	96.90	0.72	/workspace/coverage/cover_reg_top/53.xbar_random_large_delays.165654302
94.17	0.09	94.05	0.00	91.49	0.23	91.69	0.00			94.14	0.06	96.50	0.00	97.13	0.23	/workspace/coverage/cover_reg_top/31.xbar_access_same_device.204667033
94.25	0.08	94.05	0.00	91.52	0.02	92.16	0.47			94.16	0.02	96.50	0.00	97.13	0.00	/workspace/coverage/default/2.chip_sw_flash_init.1539136625
94.34	0.08	94.05	0.00	91.52	0.01	92.61	0.45			94.16	0.00	96.50	0.00	97.17	0.04	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2026025443
94.41	0.07	94.05	0.00	91.52	0.00	92.61	0.00			94.16	0.00	96.50	0.00	97.60	0.43	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.3217681818
94.48	0.07	94.05	0.00	91.72	0.20	92.62	0.01			94.39	0.23	96.50	0.00	97.60	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3562434069
94.55	0.07	94.05	0.00	92.13	0.41	92.62	0.00			94.39	0.00	96.50	0.00	97.60	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.3970417420
94.61	0.06	94.05	0.00	92.13	0.00	92.99	0.37			94.39	0.00	96.50	0.00	97.60	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.406003444
94.67	0.06	94.17	0.12	92.16	0.03	93.02	0.03			94.39	0.01	96.68	0.17	97.61	0.01	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4141305799
94.73	0.06	94.24	0.07	92.28	0.12	93.08	0.07			94.49	0.10	96.68	0.00	97.61	0.00	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2502969167
94.78	0.05	94.30	0.07	92.43	0.15	93.12	0.04			94.55	0.06	96.68	0.00	97.61	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1798969969
94.83	0.05	94.30	0.00	92.45	0.02	93.13	0.01			94.55	0.00	96.68	0.00	97.90	0.28	/workspace/coverage/default/0.chip_sw_alert_test.2478829960
94.88	0.05	94.30	0.00	92.47	0.03	93.39	0.27			94.55	0.00	96.68	0.00	97.90	0.00	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3266660231
94.93	0.05	94.34	0.04	92.50	0.02	93.41	0.02			94.56	0.02	96.85	0.17	97.91	0.01	/workspace/coverage/default/35.chip_sw_all_escalation_resets.1650678314
94.98	0.05	94.41	0.07	92.64	0.14	93.41	0.00			94.65	0.08	96.85	0.00	97.91	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1534342110
95.02	0.05	94.44	0.03	92.64	0.01	93.43	0.02			94.65	0.01	97.03	0.17	97.96	0.05	/workspace/coverage/default/19.chip_sw_all_escalation_resets.4228220083
95.07	0.05	94.44	0.00	92.67	0.03	93.43	0.00			94.65	0.00	97.03	0.00	98.20	0.25	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.4272571254
95.11	0.04	94.44	0.00	92.67	0.00	93.65	0.22			94.65	0.00	97.03	0.00	98.20	0.00	/workspace/coverage/default/1.chip_sw_kmac_idle.4099374180
95.14	0.04	94.44	0.00	92.68	0.01	93.69	0.04			94.65	0.00	97.20	0.17	98.20	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.982614471
95.18	0.04	94.44	0.01	92.69	0.01	93.69	0.01			94.66	0.01	97.38	0.17	98.21	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.1352936444
95.21	0.04	94.45	0.01	92.70	0.01	93.69	0.00			94.67	0.01	97.55	0.17	98.23	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3699741967
95.25	0.03	94.45	0.00	92.70	0.00	93.89	0.20			94.67	0.00	97.55	0.00	98.23	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2589586624
95.28	0.03	94.45	0.00	92.90	0.20	93.89	0.00			94.67	0.00	97.55	0.00	98.23	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1743715798
95.31	0.03	94.47	0.02	92.92	0.02	94.02	0.13			94.69	0.02	97.55	0.00	98.23	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2755343568
95.34	0.03	94.47	0.00	92.94	0.02	94.02	0.00			94.70	0.02	97.55	0.00	98.37	0.14	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1295897858
95.37	0.03	94.47	0.00	92.94	0.00	94.02	0.01			94.70	0.00	97.73	0.17	98.37	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1502160235
95.40	0.03	94.47	0.00	92.94	0.00	94.20	0.17			94.70	0.00	97.73	0.00	98.37	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1315794785
95.43	0.03	94.47	0.00	93.10	0.16	94.20	0.00			94.70	0.00	97.73	0.00	98.37	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.2013221824
95.45	0.03	94.47	0.00	93.10	0.00	94.35	0.16			94.70	0.00	97.73	0.00	98.37	0.00	/workspace/coverage/default/2.chip_sw_aes_entropy.1041886468
95.48	0.03	94.54	0.07	93.13	0.03	94.36	0.01			94.75	0.05	97.73	0.00	98.37	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3176758421
95.50	0.03	94.60	0.07	93.18	0.05	94.36	0.00			94.78	0.03	97.73	0.00	98.37	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2541067219
95.53	0.02	94.68	0.07	93.18	0.00	94.42	0.06			94.79	0.01	97.73	0.00	98.37	0.00	/workspace/coverage/default/3.chip_tap_straps_rma.1320197060
95.55	0.02	94.73	0.06	93.23	0.05	94.42	0.01			94.81	0.02	97.73	0.00	98.37	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3052433278
95.57	0.02	94.73	0.00	93.23	0.00	94.55	0.12			94.81	0.00	97.73	0.00	98.37	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3257868311
95.59	0.02	94.76	0.03	93.27	0.04	94.55	0.01			94.83	0.02	97.73	0.00	98.37	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.492013518
95.60	0.02	94.76	0.00	93.33	0.05	94.55	0.00			94.83	0.00	97.73	0.00	98.41	0.05	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1350356364
95.62	0.02	94.76	0.00	93.33	0.00	94.65	0.09			94.83	0.00	97.73	0.00	98.41	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.4059088092
95.63	0.02	94.78	0.01	93.37	0.05	94.66	0.02			94.85	0.02	97.73	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.4241973835
95.65	0.01	94.78	0.00	93.44	0.07	94.66	0.00			94.86	0.02	97.73	0.00	98.41	0.00	/workspace/coverage/cover_reg_top/77.xbar_stress_all.3504491866
95.66	0.01	94.78	0.00	93.44	0.00	94.66	0.00			94.86	0.00	97.73	0.00	98.50	0.08	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.35259400
95.67	0.01	94.78	0.00	93.50	0.06	94.66	0.00			94.86	0.00	97.73	0.00	98.51	0.01	/workspace/coverage/cover_reg_top/28.chip_tl_errors.737158730
95.69	0.01	94.78	0.00	93.50	0.00	94.73	0.07			94.86	0.00	97.73	0.00	98.51	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1448523358
95.70	0.01	94.78	0.00	93.57	0.07	94.73	0.00			94.86	0.00	97.73	0.00	98.51	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.2668276323
95.71	0.01	94.78	0.00	93.57	0.00	94.80	0.06			94.86	0.00	97.73	0.00	98.51	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4164978065
95.72	0.01	94.78	0.00	93.63	0.06	94.80	0.00			94.86	0.00	97.73	0.00	98.51	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.309948751
95.73	0.01	94.79	0.02	93.64	0.01	94.81	0.01			94.88	0.02	97.73	0.00	98.51	0.00	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2945597471
95.73	0.01	94.82	0.02	93.64	0.01	94.82	0.01			94.90	0.02	97.73	0.00	98.51	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1530754408
95.74	0.01	94.82	0.00	93.64	0.00	94.82	0.00			94.90	0.00	97.73	0.00	98.55	0.05	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.789169014
95.75	0.01	94.82	0.00	93.69	0.05	94.82	0.00			94.90	0.00	97.73	0.00	98.55	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.931706362
95.76	0.01	94.82	0.00	93.71	0.02	94.83	0.02			94.90	0.00	97.73	0.00	98.55	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_aliasing.2870769579
95.76	0.01	94.82	0.00	93.72	0.01	94.83	0.00			94.90	0.00	97.73	0.00	98.59	0.04	/workspace/coverage/cover_reg_top/55.xbar_stress_all.3595990329
95.77	0.01	94.82	0.00	93.72	0.00	94.88	0.04			94.90	0.00	97.73	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3051481120
95.78	0.01	94.83	0.01	93.72	0.01	94.90	0.03			94.90	0.00	97.73	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1637225833
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96.01	0.01	94.87	0.00	93.97	0.00	95.10	0.00			94.90	0.00	97.73	0.00	99.48	0.01	/workspace/coverage/default/58.chip_sw_all_escalation_resets.1313496145
96.01	0.01	94.87	0.00	93.97	0.00	95.10	0.00			94.90	0.00	97.73	0.00	99.49	0.01	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.4250747768
96.01	0.01	94.87	0.00	93.97	0.00	95.10	0.00			94.90	0.00	97.73	0.00	99.51	0.01	/workspace/coverage/default/71.chip_sw_all_escalation_resets.1126835270
96.01	0.01	94.87	0.00	93.97	0.00	95.10	0.00			94.90	0.00	97.73	0.00	99.52	0.01	/workspace/coverage/default/76.chip_sw_all_escalation_resets.2717093730
96.01	0.01	94.87	0.00	93.97	0.00	95.10	0.00			94.90	0.00	97.73	0.00	99.53	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.2509815939
96.02	0.01	94.87	0.00	93.97	0.00	95.10	0.00			94.90	0.00	97.73	0.00	99.54	0.01	/workspace/coverage/default/84.chip_sw_all_escalation_resets.150176406
96.02	0.01	94.87	0.00	93.98	0.01	95.10	0.00			94.90	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.220212259
96.02	0.01	94.87	0.00	93.99	0.01	95.10	0.00			94.90	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3772117383
96.02	0.01	94.87	0.00	94.00	0.01	95.10	0.00			94.90	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.807800448
96.02	0.01	94.87	0.00	94.01	0.01	95.10	0.00			94.90	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1358162220
96.03	0.01	94.87	0.00	94.01	0.00	95.11	0.01			94.90	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3727983329
96.03	0.01	94.87	0.01	94.01	0.00	95.11	0.01			94.90	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3743338603
96.03	0.01	94.88	0.01	94.02	0.01	95.11	0.00			94.90	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1851041722
96.03	0.01	94.88	0.01	94.02	0.01	95.11	0.00			94.90	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.2362173916
96.03	0.01	94.88	0.00	94.02	0.00	95.12	0.01			94.90	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_flash_init.2297411870
96.03	0.01	94.88	0.00	94.02	0.00	95.13	0.01			94.90	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3206464959
96.04	0.01	94.88	0.00	94.02	0.00	95.14	0.01			94.90	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.4200589009
96.04	0.01	94.88	0.00	94.02	0.00	95.14	0.00			94.90	0.01	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.44362205
96.04	0.01	94.88	0.00	94.02	0.00	95.14	0.00			94.91	0.01	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.4286491602
96.04	0.01	94.88	0.00	94.03	0.01	95.14	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2078923362
96.04	0.01	94.88	0.00	94.04	0.01	95.14	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/4.chip_tl_errors.444067876
96.04	0.01	94.88	0.00	94.04	0.01	95.14	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.3984785500
96.04	0.01	94.88	0.00	94.05	0.01	95.14	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/2.chip_sw_gpio.1791974755
96.04	0.01	94.88	0.00	94.05	0.00	95.15	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3655783957
96.05	0.01	94.88	0.00	94.05	0.00	95.16	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4091722933
96.05	0.01	94.88	0.00	94.05	0.00	95.16	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1097476014
96.05	0.01	94.89	0.01	94.05	0.00	95.16	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.465038478
96.05	0.01	94.90	0.01	94.05	0.00	95.16	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2381434015
96.05	0.01	94.90	0.00	94.05	0.00	95.17	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1689416153
96.05	0.01	94.90	0.00	94.05	0.00	95.17	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.182900094
96.05	0.01	94.90	0.00	94.05	0.00	95.18	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2200109995
96.05	0.01	94.90	0.00	94.05	0.00	95.18	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.670427876
96.05	0.01	94.90	0.00	94.05	0.00	95.19	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2959034892
96.05	0.01	94.90	0.00	94.05	0.01	95.19	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.1054156144
96.05	0.01	94.90	0.00	94.06	0.01	95.19	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.4086957116
96.05	0.01	94.90	0.00	94.06	0.01	95.19	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.2456134662
96.05	0.01	94.90	0.00	94.06	0.01	95.19	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.3933101547
96.06	0.01	94.90	0.00	94.07	0.01	95.19	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.4104655908
96.06	0.01	94.90	0.00	94.07	0.01	95.19	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2123363990
96.06	0.01	94.90	0.00	94.07	0.01	95.19	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3719905561
96.06	0.01	94.90	0.00	94.08	0.01	95.19	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2399181790
96.06	0.01	94.90	0.00	94.08	0.01	95.19	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1831505113
96.06	0.01	94.90	0.00	94.08	0.01	95.19	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2925763891
96.06	0.01	94.90	0.00	94.09	0.01	95.19	0.00			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1252153652
96.06	0.01	94.90	0.00	94.09	0.00	95.19	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3116428619
96.06	0.01	94.90	0.00	94.09	0.00	95.19	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2395463013
96.06	0.01	94.90	0.00	94.09	0.00	95.19	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.293855638
96.06	0.01	94.90	0.00	94.09	0.00	95.20	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1245547282
96.06	0.01	94.90	0.00	94.09	0.00	95.20	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1255756506
96.06	0.01	94.90	0.00	94.09	0.00	95.20	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2394880458
96.06	0.01	94.90	0.00	94.09	0.00	95.20	0.01			94.91	0.00	97.73	0.00	99.54	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3214132452

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3493251072
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2649811649
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3383229695
/workspace/coverage/cover_reg_top/0.chip_csr_rw.745522662
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.626879305
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3167095674
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1248958441
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1654338936
/workspace/coverage/cover_reg_top/0.xbar_error_random.1153071537
/workspace/coverage/cover_reg_top/0.xbar_random.2499022522
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2703675049
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.313315454
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3460542396
/workspace/coverage/cover_reg_top/0.xbar_same_source.2774896433
/workspace/coverage/cover_reg_top/0.xbar_smoke.4024625664
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.164056824
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1141767743
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2758567278
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1047692055
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1525465470
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3203031322
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1890441178
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1683384956
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3015433762
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.66436979
/workspace/coverage/cover_reg_top/1.chip_csr_rw.32979784
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2934800356
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1497376221
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2197173512
/workspace/coverage/cover_reg_top/1.chip_tl_errors.776157816
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.3893342488
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1273654573
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.41899869
/workspace/coverage/cover_reg_top/1.xbar_error_random.57302729
/workspace/coverage/cover_reg_top/1.xbar_random.687105698
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.4053662487
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.472916169
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.253099037
/workspace/coverage/cover_reg_top/1.xbar_same_source.1823228928
/workspace/coverage/cover_reg_top/1.xbar_smoke.1341642057
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3169805625
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.455884130
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1258618518
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2042399323
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2094812081
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.643948024
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1967485969
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3675564672
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3890009824
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.4006862679
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2920545297
/workspace/coverage/cover_reg_top/10.xbar_error_random.3911174560
/workspace/coverage/cover_reg_top/10.xbar_random.1732559629
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1383658272
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1687121261
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1660233848
/workspace/coverage/cover_reg_top/10.xbar_same_source.2447611634
/workspace/coverage/cover_reg_top/10.xbar_smoke.1808599884
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2494041750
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2247609742
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.513859441
/workspace/coverage/cover_reg_top/10.xbar_stress_all.4162932508
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.384065848
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.186315433
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.29315162
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1495569063
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2290361243
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.414169772
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1246805228
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1733310591
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3856540823
/workspace/coverage/cover_reg_top/11.xbar_error_random.1843483296
/workspace/coverage/cover_reg_top/11.xbar_random.3840292896
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3329651441
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1949515390
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1097440696
/workspace/coverage/cover_reg_top/11.xbar_same_source.713510977
/workspace/coverage/cover_reg_top/11.xbar_smoke.50384022
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.384252470
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.45987367
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2221676470
/workspace/coverage/cover_reg_top/11.xbar_stress_all.222500901
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3535787033
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2577689886
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1300261204
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.4280356446
/workspace/coverage/cover_reg_top/12.chip_csr_rw.817783700
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1104570266
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2331225516
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3422834082
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1648561487
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3721601434
/workspace/coverage/cover_reg_top/12.xbar_error_random.515405392
/workspace/coverage/cover_reg_top/12.xbar_random.945526274
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3284159544
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1965582415
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3354087436
/workspace/coverage/cover_reg_top/12.xbar_same_source.3007168173
/workspace/coverage/cover_reg_top/12.xbar_smoke.182627075
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2191145588
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2650228689
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2445703327
/workspace/coverage/cover_reg_top/12.xbar_stress_all.3190738196
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1730389647
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2994380351
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2850890283
/workspace/coverage/cover_reg_top/13.chip_csr_rw.984108630
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2424913883
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3807809291
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3073360700
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2593615924
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3812049031
/workspace/coverage/cover_reg_top/13.xbar_error_random.4113721802
/workspace/coverage/cover_reg_top/13.xbar_random.1583974345
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.4213288647
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.354626399
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2746573315
/workspace/coverage/cover_reg_top/13.xbar_same_source.2295966833
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/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1271216471
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4034701349
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3889459738
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/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.4097244843
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2967043622
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/workspace/coverage/default/2.rom_e2e_shutdown_output.4077817458
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/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115404265
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441121490
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.656987623
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/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1456890144
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/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2728214514
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/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3636744622
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/workspace/coverage/default/3.chip_tap_straps_testunlock0.795328974
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1657823402
/workspace/coverage/default/31.chip_sw_all_escalation_resets.1209692598
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2212471899
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2393304124
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.4050068781
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2122396574
/workspace/coverage/default/37.chip_sw_all_escalation_resets.4148647303
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1594735976
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2072404056
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1764668031
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.4185886994
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1763793072
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3455524990
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.820925678
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.782023483
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3788103244
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2877971973
/workspace/coverage/default/4.chip_sw_uart_tx_rx.1819245602
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.834938706
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.191675543
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3779609548
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.543630675
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3479411425
/workspace/coverage/default/4.chip_tap_straps_dev.787360158
/workspace/coverage/default/4.chip_tap_straps_rma.763387424
/workspace/coverage/default/4.chip_tap_straps_testunlock0.50808419
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3170860728
/workspace/coverage/default/43.chip_sw_all_escalation_resets.498260857
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2306817318
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1520523476
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3505190621
/workspace/coverage/default/45.chip_sw_all_escalation_resets.2752085232
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1016622505
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2123824733
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.541676990
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3010408832
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2637200047
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2314003549
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.506527952
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1983527190
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3064125264
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1848408507
/workspace/coverage/default/50.chip_sw_all_escalation_resets.4163658714
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1491089377
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3290059718
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3325170819
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3497089236
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2216351575
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3455328432
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771832249
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3742127744
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4100078392
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2606631208
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2483292999
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.699895420
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3596280018
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3586084147
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1982213357
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2650565779
/workspace/coverage/default/63.chip_sw_all_escalation_resets.564578044
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1328068604
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1956913101
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3539158948
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1771801247
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1778570616
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2287565228
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2778926982
/workspace/coverage/default/67.chip_sw_all_escalation_resets.4046381713
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3902067496
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2172182477
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1735649773
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3671647664
/workspace/coverage/default/7.chip_sw_all_escalation_resets.1432711855
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.66492317
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3056801542
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1583174532
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2325823289
/workspace/coverage/default/70.chip_sw_all_escalation_resets.4171889169
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4050278434
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.347028553
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2390736733
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3348703761
/workspace/coverage/default/73.chip_sw_all_escalation_resets.4231865711
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.742345032
/workspace/coverage/default/74.chip_sw_all_escalation_resets.3261953661
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3701880901
/workspace/coverage/default/75.chip_sw_all_escalation_resets.907413001
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.555241165
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.46308106
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3875740785
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1919560452
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.257129264
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.981112506
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3111883022
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.650064616
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.314355593
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.658662805
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3321980314
/workspace/coverage/default/80.chip_sw_all_escalation_resets.4091957846
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3347281779
/workspace/coverage/default/81.chip_sw_all_escalation_resets.1873469126
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3150988386
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1708084783
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1823792242
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3825610711
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3959215233
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2556066250
/workspace/coverage/default/85.chip_sw_all_escalation_resets.398219833
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.304769779
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3731876717
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4023450837
/workspace/coverage/default/87.chip_sw_all_escalation_resets.574391645
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333100174
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3790061952
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.101143994
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1671686325
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.66231888
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1704068829
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3813358102
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.537848380
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3418855431
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1758816666
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3400499240
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2049009559
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3202881875
/workspace/coverage/default/95.chip_sw_all_escalation_resets.187209572
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1292037062
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1394873472
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2519151808
/workspace/coverage/default/99.chip_sw_all_escalation_resets.4043129185
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.499330735
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.218621436
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.824620571
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3646409706
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2142305716
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1831059956
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2779484947
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.10551965

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Total test records in report: 2885

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3043602894			Jun 28 08:08:56 PM PDT 24	Jun 28 08:18:53 PM PDT 24	4692138028 ps
T5	/workspace/coverage/default/69.chip_sw_all_escalation_resets.1735649773			Jun 28 08:31:53 PM PDT 24	Jun 28 08:45:47 PM PDT 24	5776881688 ps
T6	/workspace/coverage/default/0.rom_e2e_shutdown_output.471233466			Jun 28 08:06:15 PM PDT 24	Jun 28 09:12:17 PM PDT 24	27165423859 ps
T42	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.4198827421			Jun 28 08:24:30 PM PDT 24	Jun 28 08:29:44 PM PDT 24	2762367918 ps
T53	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1697399930			Jun 28 08:07:06 PM PDT 24	Jun 28 09:07:52 PM PDT 24	11608357591 ps
T19	/workspace/coverage/default/2.chip_sw_flash_init.1539136625			Jun 28 08:15:59 PM PDT 24	Jun 28 08:49:34 PM PDT 24	19324603388 ps
T20	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1815283822			Jun 28 08:04:38 PM PDT 24	Jun 28 08:18:21 PM PDT 24	7145419082 ps
T55	/workspace/coverage/default/2.chip_jtag_mem_access.1393739630			Jun 28 08:13:33 PM PDT 24	Jun 28 08:35:43 PM PDT 24	14066436868 ps
T17	/workspace/coverage/default/40.chip_sw_all_escalation_resets.4002988025			Jun 28 08:31:46 PM PDT 24	Jun 28 08:43:31 PM PDT 24	4983392680 ps
T68	/workspace/coverage/default/3.chip_tap_straps_prod.1863599695			Jun 28 08:22:35 PM PDT 24	Jun 28 08:35:49 PM PDT 24	7987020089 ps
T56	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3919524905			Jun 28 08:04:15 PM PDT 24	Jun 28 08:19:27 PM PDT 24	12098635141 ps
T111	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3960683824			Jun 28 08:05:45 PM PDT 24	Jun 28 08:26:48 PM PDT 24	6539834274 ps
T18	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3718709422			Jun 28 08:29:17 PM PDT 24	Jun 28 08:37:09 PM PDT 24	4439531102 ps
T373	/workspace/coverage/default/2.chip_sw_aes_entropy.1041886468			Jun 28 08:18:01 PM PDT 24	Jun 28 08:22:08 PM PDT 24	2732700118 ps
T21	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2301892530			Jun 28 08:04:02 PM PDT 24	Jun 28 08:07:46 PM PDT 24	2894767306 ps
T27	/workspace/coverage/default/1.chip_sw_gpio.633080103			Jun 28 08:06:42 PM PDT 24	Jun 28 08:14:18 PM PDT 24	3285951970 ps
T188	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3820638355			Jun 28 08:05:14 PM PDT 24	Jun 28 08:13:10 PM PDT 24	3713399608 ps
T119	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2672424047			Jun 28 08:19:48 PM PDT 24	Jun 28 08:24:29 PM PDT 24	2426780192 ps
T54	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.761080570			Jun 28 08:12:26 PM PDT 24	Jun 28 09:12:48 PM PDT 24	15810237009 ps
T45	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2128098694			Jun 28 08:18:25 PM PDT 24	Jun 28 08:29:52 PM PDT 24	5804489840 ps
T120	/workspace/coverage/default/0.chip_sw_edn_sw_mode.3130406435			Jun 28 08:04:41 PM PDT 24	Jun 28 08:35:39 PM PDT 24	7786768118 ps
T177	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2502969167			Jun 28 08:26:10 PM PDT 24	Jun 28 08:37:56 PM PDT 24	3980277300 ps
T189	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.224169796			Jun 28 08:16:55 PM PDT 24	Jun 28 08:30:06 PM PDT 24	7654807848 ps
T62	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2380486162			Jun 28 08:06:28 PM PDT 24	Jun 28 08:08:30 PM PDT 24	2812429019 ps
T121	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3815675801			Jun 28 08:05:09 PM PDT 24	Jun 28 09:31:38 PM PDT 24	15739205140 ps
T110	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.977952737			Jun 28 07:59:51 PM PDT 24	Jun 28 08:21:04 PM PDT 24	7204855135 ps
T124	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3788103244			Jun 28 08:23:32 PM PDT 24	Jun 28 08:35:41 PM PDT 24	7335709264 ps
T147	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3788223067			Jun 28 08:16:34 PM PDT 24	Jun 28 08:46:43 PM PDT 24	12544769412 ps
T1	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3677851898			Jun 28 08:22:59 PM PDT 24	Jun 28 08:47:24 PM PDT 24	25217200872 ps
T99	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.465038478			Jun 28 08:06:58 PM PDT 24	Jun 28 08:22:23 PM PDT 24	4457401464 ps
T66	/workspace/coverage/default/4.chip_tap_straps_rma.763387424			Jun 28 08:23:56 PM PDT 24	Jun 28 08:28:23 PM PDT 24	3862725160 ps
T100	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2999243876			Jun 28 08:08:14 PM PDT 24	Jun 28 08:34:09 PM PDT 24	6555196296 ps
T101	/workspace/coverage/default/2.chip_sw_otbn_smoketest.2525348042			Jun 28 08:23:06 PM PDT 24	Jun 28 08:46:46 PM PDT 24	7805984092 ps
T102	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2539970103			Jun 28 08:10:49 PM PDT 24	Jun 28 08:18:36 PM PDT 24	3119726392 ps
T103	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3222567065			Jun 28 08:16:28 PM PDT 24	Jun 28 08:28:00 PM PDT 24	3946402160 ps
T104	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1462533249			Jun 28 08:03:06 PM PDT 24	Jun 28 08:24:25 PM PDT 24	8266590168 ps
T105	/workspace/coverage/default/2.chip_sw_kmac_smoketest.1739262320			Jun 28 08:23:30 PM PDT 24	Jun 28 08:27:35 PM PDT 24	2669065500 ps
T106	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3727983329			Jun 28 08:02:55 PM PDT 24	Jun 28 08:58:48 PM PDT 24	25742403491 ps
T60	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2589586624			Jun 28 08:03:14 PM PDT 24	Jun 28 08:08:18 PM PDT 24	3162758724 ps
T61	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3308566000			Jun 28 08:04:07 PM PDT 24	Jun 28 08:07:07 PM PDT 24	3362393575 ps
T281	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.349454856			Jun 28 08:18:33 PM PDT 24	Jun 28 08:21:33 PM PDT 24	3321366696 ps
T282	/workspace/coverage/default/1.chip_sw_hmac_smoketest.1667293573			Jun 28 08:13:23 PM PDT 24	Jun 28 08:19:32 PM PDT 24	2868724140 ps
T283	/workspace/coverage/default/1.chip_sw_aes_idle.2921194210			Jun 28 08:08:18 PM PDT 24	Jun 28 08:12:56 PM PDT 24	3123499516 ps
T855	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.4016359999			Jun 28 08:01:54 PM PDT 24	Jun 28 08:07:56 PM PDT 24	3250967436 ps
T856	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2844137481			Jun 28 08:05:53 PM PDT 24	Jun 28 08:11:04 PM PDT 24	4365556498 ps
T117	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3266660231			Jun 28 08:07:46 PM PDT 24	Jun 28 08:28:43 PM PDT 24	6252465760 ps
T309	/workspace/coverage/default/35.chip_sw_all_escalation_resets.1650678314			Jun 28 08:29:27 PM PDT 24	Jun 28 08:42:28 PM PDT 24	4874235072 ps
T169	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1218803030			Jun 28 08:24:57 PM PDT 24	Jun 28 08:35:46 PM PDT 24	4084888462 ps
T113	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3267113822			Jun 28 08:17:53 PM PDT 24	Jun 28 08:38:22 PM PDT 24	11241944640 ps
T107	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3199746854			Jun 28 08:10:22 PM PDT 24	Jun 28 09:01:45 PM PDT 24	19110796719 ps
T313	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.283311933			Jun 28 07:59:47 PM PDT 24	Jun 28 08:16:43 PM PDT 24	6084811651 ps
T122	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3686548018			Jun 28 08:20:32 PM PDT 24	Jun 28 08:29:14 PM PDT 24	5584034604 ps
T314	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3568377991			Jun 28 08:14:02 PM PDT 24	Jun 28 08:59:12 PM PDT 24	14447076892 ps
T315	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3003817889			Jun 28 08:14:05 PM PDT 24	Jun 28 08:24:52 PM PDT 24	5239120200 ps
T48	/workspace/coverage/default/1.chip_sw_spi_device_tpm.2810683354			Jun 28 08:04:16 PM PDT 24	Jun 28 08:09:55 PM PDT 24	3074816306 ps
T209	/workspace/coverage/default/75.chip_sw_all_escalation_resets.907413001			Jun 28 08:37:59 PM PDT 24	Jun 28 08:49:44 PM PDT 24	6061174452 ps
T179	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.699913836			Jun 28 08:04:06 PM PDT 24	Jun 28 08:08:01 PM PDT 24	2955165126 ps
T22	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3562434069			Jun 28 08:05:56 PM PDT 24	Jun 28 08:10:57 PM PDT 24	3357826885 ps
T507	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1879458961			Jun 28 08:06:27 PM PDT 24	Jun 28 08:14:43 PM PDT 24	5391332956 ps
T318	/workspace/coverage/default/2.chip_sw_otbn_randomness.3768237166			Jun 28 08:17:31 PM PDT 24	Jun 28 08:32:21 PM PDT 24	6031036564 ps
T151	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1733803937			Jun 28 08:28:38 PM PDT 24	Jun 28 08:35:41 PM PDT 24	4088681672 ps
T857	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3742467122			Jun 28 08:23:36 PM PDT 24	Jun 28 08:26:54 PM PDT 24	2866164676 ps
T114	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1009973891			Jun 28 08:20:14 PM PDT 24	Jun 28 08:31:08 PM PDT 24	4443316884 ps
T180	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.782023483			Jun 28 08:25:33 PM PDT 24	Jun 28 08:33:54 PM PDT 24	5281620711 ps
T858	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3056801542			Jun 28 08:25:40 PM PDT 24	Jun 28 08:38:46 PM PDT 24	10498901215 ps
T306	/workspace/coverage/default/4.chip_sw_uart_tx_rx.1819245602			Jun 28 08:23:12 PM PDT 24	Jun 28 08:34:37 PM PDT 24	4386636280 ps
T506	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.4250747768			Jun 28 08:30:08 PM PDT 24	Jun 28 08:34:46 PM PDT 24	3505614274 ps
T2	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.243499813			Jun 28 08:27:39 PM PDT 24	Jun 28 08:34:51 PM PDT 24	7296817172 ps
T249	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2381434015			Jun 28 08:03:06 PM PDT 24	Jun 28 08:07:51 PM PDT 24	2991948940 ps
T252	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3405525088			Jun 28 08:16:26 PM PDT 24	Jun 28 09:14:31 PM PDT 24	39575566704 ps
T859	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1031348823			Jun 28 08:22:26 PM PDT 24	Jun 28 08:43:32 PM PDT 24	5225407152 ps
T731	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2482124976			Jun 28 08:26:18 PM PDT 24	Jun 28 08:33:37 PM PDT 24	3945439400 ps
T253	/workspace/coverage/default/1.chip_plic_all_irqs_0.2233226304			Jun 28 08:06:41 PM PDT 24	Jun 28 08:27:46 PM PDT 24	5626297720 ps
T143	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.424597684			Jun 28 08:06:40 PM PDT 24	Jun 28 09:10:32 PM PDT 24	17179683444 ps
T680	/workspace/coverage/default/10.chip_sw_all_escalation_resets.181505027			Jun 28 08:28:44 PM PDT 24	Jun 28 08:40:42 PM PDT 24	6251171596 ps
T158	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.901792875			Jun 28 08:17:53 PM PDT 24	Jun 28 08:19:44 PM PDT 24	2392420040 ps
T860	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1448523358			Jun 28 08:12:06 PM PDT 24	Jun 28 08:22:40 PM PDT 24	5542702302 ps
T123	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3624032352			Jun 28 08:24:01 PM PDT 24	Jun 28 08:38:17 PM PDT 24	6799465182 ps
T112	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.331864895			Jun 28 08:11:13 PM PDT 24	Jun 28 08:21:48 PM PDT 24	5791267796 ps
T355	/workspace/coverage/default/4.chip_sw_all_escalation_resets.1505340526			Jun 28 08:25:17 PM PDT 24	Jun 28 08:37:44 PM PDT 24	4993436328 ps
T115	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.331686710			Jun 28 08:09:03 PM PDT 24	Jun 28 08:23:11 PM PDT 24	4878160558 ps
T75	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.188756077			Jun 28 08:00:58 PM PDT 24	Jun 28 11:08:52 PM PDT 24	58160032883 ps
T162	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1819739911			Jun 28 08:05:29 PM PDT 24	Jun 28 09:43:18 PM PDT 24	50109119732 ps
T241	/workspace/coverage/default/19.chip_sw_all_escalation_resets.4228220083			Jun 28 08:26:24 PM PDT 24	Jun 28 08:35:41 PM PDT 24	4985630522 ps
T210	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3513508504			Jun 28 08:01:03 PM PDT 24	Jun 28 08:19:01 PM PDT 24	7369993216 ps
T238	/workspace/coverage/default/12.chip_sw_all_escalation_resets.4077856222			Jun 28 08:27:01 PM PDT 24	Jun 28 08:36:48 PM PDT 24	5176231740 ps
T108	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3939785441			Jun 28 08:02:38 PM PDT 24	Jun 28 09:43:17 PM PDT 24	32500616304 ps
T261	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2457152403			Jun 28 08:08:19 PM PDT 24	Jun 28 09:18:44 PM PDT 24	15712940404 ps
T262	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2432106650			Jun 28 08:05:51 PM PDT 24	Jun 28 08:35:51 PM PDT 24	13640881788 ps
T263	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2731424385			Jun 28 08:07:58 PM PDT 24	Jun 28 08:13:00 PM PDT 24	3599617203 ps
T255	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1781415626			Jun 28 08:11:51 PM PDT 24	Jun 28 09:19:46 PM PDT 24	16647592936 ps
T264	/workspace/coverage/default/1.chip_sw_aes_enc.2739954695			Jun 28 08:04:48 PM PDT 24	Jun 28 08:09:22 PM PDT 24	3300615648 ps
T46	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1694993668			Jun 28 08:06:21 PM PDT 24	Jun 28 08:14:35 PM PDT 24	6051865432 ps
T242	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2299184888			Jun 28 08:17:25 PM PDT 24	Jun 28 08:31:54 PM PDT 24	6164873920 ps
T861	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.705431708			Jun 28 08:02:59 PM PDT 24	Jun 28 08:07:39 PM PDT 24	2809161505 ps
T692	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3030961395			Jun 28 08:08:59 PM PDT 24	Jun 28 08:17:09 PM PDT 24	3889196040 ps
T118	/workspace/coverage/default/1.chip_sw_edn_boot_mode.2676014077			Jun 28 08:06:16 PM PDT 24	Jun 28 08:16:39 PM PDT 24	3605792760 ps
T862	/workspace/coverage/default/1.chip_sw_kmac_idle.4099374180			Jun 28 08:09:24 PM PDT 24	Jun 28 08:14:10 PM PDT 24	2670686184 ps
T628	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3455524990			Jun 28 08:23:39 PM PDT 24	Jun 28 09:32:12 PM PDT 24	17902870004 ps
T337	/workspace/coverage/default/2.chip_sw_aon_timer_irq.3533674324			Jun 28 08:18:14 PM PDT 24	Jun 28 08:24:12 PM PDT 24	3967508716 ps
T167	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2383839747			Jun 28 08:05:27 PM PDT 24	Jun 28 08:50:15 PM PDT 24	31209478595 ps
T514	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2488084170			Jun 28 08:04:31 PM PDT 24	Jun 28 08:13:43 PM PDT 24	8634297932 ps
T513	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2029994338			Jun 28 08:32:56 PM PDT 24	Jun 28 08:45:29 PM PDT 24	5645931580 ps
T388	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.257129264			Jun 28 08:32:00 PM PDT 24	Jun 28 08:40:55 PM PDT 24	3851834460 ps
T348	/workspace/coverage/default/18.chip_sw_all_escalation_resets.3240639321			Jun 28 08:28:49 PM PDT 24	Jun 28 08:37:27 PM PDT 24	5614296138 ps
T239	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3671647664			Jun 28 08:28:15 PM PDT 24	Jun 28 08:33:47 PM PDT 24	3327516322 ps
T152	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3705584724			Jun 28 08:02:37 PM PDT 24	Jun 28 08:42:14 PM PDT 24	13443499728 ps
T863	/workspace/coverage/default/2.rom_e2e_asm_init_rma.2042461034			Jun 28 08:26:00 PM PDT 24	Jun 28 09:28:33 PM PDT 24	15129050000 ps
T864	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.247849587			Jun 28 08:08:44 PM PDT 24	Jun 28 08:12:42 PM PDT 24	2853393550 ps
T28	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.4215977502			Jun 28 08:31:41 PM PDT 24	Jun 28 08:42:57 PM PDT 24	4327486882 ps
T865	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1983527190			Jun 28 08:25:36 PM PDT 24	Jun 28 08:32:53 PM PDT 24	6752252761 ps
T138	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3185886785			Jun 28 08:07:07 PM PDT 24	Jun 28 11:50:28 PM PDT 24	78394065006 ps
T325	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1914613978			Jun 28 08:27:15 PM PDT 24	Jun 28 09:08:22 PM PDT 24	13490860940 ps
T3	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.815975842			Jun 28 08:04:30 PM PDT 24	Jun 28 08:34:25 PM PDT 24	24416690904 ps
T678	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3586084147			Jun 28 08:32:04 PM PDT 24	Jun 28 08:36:58 PM PDT 24	2938656748 ps
T866	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.4151419420			Jun 28 08:04:44 PM PDT 24	Jun 28 09:14:03 PM PDT 24	15798077864 ps
T116	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1731672671			Jun 28 08:07:06 PM PDT 24	Jun 28 08:18:09 PM PDT 24	3643790800 ps
T764	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3825313695			Jun 28 08:29:31 PM PDT 24	Jun 28 08:38:04 PM PDT 24	3447223344 ps
T156	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.375108869			Jun 28 08:05:33 PM PDT 24	Jun 28 08:07:40 PM PDT 24	2060067852 ps
T30	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.481498783			Jun 28 08:02:50 PM PDT 24	Jun 28 08:13:16 PM PDT 24	3955487240 ps
T76	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3579750852			Jun 28 08:02:54 PM PDT 24	Jun 28 08:10:02 PM PDT 24	3440613384 ps
T208	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1041407816			Jun 28 08:05:32 PM PDT 24	Jun 28 08:18:51 PM PDT 24	5066491288 ps
T867	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4164978065			Jun 28 08:05:23 PM PDT 24	Jun 28 08:17:13 PM PDT 24	3783737288 ps
T868	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3847754841			Jun 28 08:07:52 PM PDT 24	Jun 28 08:11:44 PM PDT 24	2988386656 ps
T670	/workspace/coverage/default/0.chip_sw_hmac_multistream.1663293629			Jun 28 08:02:59 PM PDT 24	Jun 28 08:40:17 PM PDT 24	8520917128 ps
T307	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3868075049			Jun 28 08:31:50 PM PDT 24	Jun 28 09:01:53 PM PDT 24	8387075328 ps
T265	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4077111167			Jun 28 08:05:44 PM PDT 24	Jun 28 08:07:37 PM PDT 24	2352581705 ps
T212	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.44362205			Jun 28 08:01:36 PM PDT 24	Jun 28 08:13:17 PM PDT 24	5742005871 ps
T869	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3286438538			Jun 28 08:00:32 PM PDT 24	Jun 28 08:05:10 PM PDT 24	2661033656 ps
T128	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3176758421			Jun 28 08:04:43 PM PDT 24	Jun 28 08:21:22 PM PDT 24	5683530712 ps
T653	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2723163318			Jun 28 08:17:27 PM PDT 24	Jun 28 08:22:08 PM PDT 24	2845176876 ps
T870	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2146392592			Jun 28 08:21:02 PM PDT 24	Jun 28 08:34:00 PM PDT 24	4477881306 ps
T871	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3661046138			Jun 28 08:05:58 PM PDT 24	Jun 28 08:18:01 PM PDT 24	5695650220 ps
T77	/workspace/coverage/default/1.chip_jtag_mem_access.491937453			Jun 28 07:58:05 PM PDT 24	Jun 28 08:30:37 PM PDT 24	14009298888 ps
T308	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3923803099			Jun 28 08:05:51 PM PDT 24	Jun 28 08:17:19 PM PDT 24	4431294916 ps
T671	/workspace/coverage/default/0.chip_sw_hmac_smoketest.2596684003			Jun 28 08:02:22 PM PDT 24	Jun 28 08:08:30 PM PDT 24	3124722440 ps
T340	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2505034395			Jun 28 08:04:26 PM PDT 24	Jun 28 08:15:46 PM PDT 24	3867947804 ps
T872	/workspace/coverage/default/0.rom_e2e_smoke.389028981			Jun 28 08:06:27 PM PDT 24	Jun 28 09:17:20 PM PDT 24	15007255316 ps
T873	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1456890144			Jun 28 08:24:33 PM PDT 24	Jun 28 08:32:33 PM PDT 24	7202601080 ps
T672	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1652103233			Jun 28 08:33:51 PM PDT 24	Jun 28 08:41:39 PM PDT 24	3594522844 ps
T669	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1594735976			Jun 28 08:31:48 PM PDT 24	Jun 28 08:38:38 PM PDT 24	3634062450 ps
T874	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2932414278			Jun 28 08:06:02 PM PDT 24	Jun 28 08:17:35 PM PDT 24	3850649694 ps
T205	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.898338778			Jun 28 08:07:53 PM PDT 24	Jun 28 08:38:53 PM PDT 24	7668083912 ps
T706	/workspace/coverage/default/58.chip_sw_all_escalation_resets.1313496145			Jun 28 08:31:28 PM PDT 24	Jun 28 08:43:17 PM PDT 24	5461340538 ps
T681	/workspace/coverage/default/23.chip_sw_all_escalation_resets.1785976869			Jun 28 08:27:24 PM PDT 24	Jun 28 08:36:50 PM PDT 24	4814966224 ps
T243	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1706494493			Jun 28 08:06:43 PM PDT 24	Jun 28 08:20:26 PM PDT 24	6756557230 ps
T875	/workspace/coverage/default/1.chip_sw_hmac_oneshot.544228936			Jun 28 08:04:44 PM PDT 24	Jun 28 08:10:21 PM PDT 24	2208219960 ps
T633	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.66492317			Jun 28 08:26:26 PM PDT 24	Jun 28 10:00:19 PM PDT 24	25706432888 ps
T667	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1016622505			Jun 28 08:28:49 PM PDT 24	Jun 28 08:37:08 PM PDT 24	4183101816 ps
T635	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2216351575			Jun 28 08:30:02 PM PDT 24	Jun 28 08:37:04 PM PDT 24	3673101500 ps
T240	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3052851766			Jun 28 08:08:36 PM PDT 24	Jun 28 08:29:00 PM PDT 24	5310002426 ps
T876	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.994661981			Jun 28 08:04:25 PM PDT 24	Jun 28 08:08:56 PM PDT 24	2996225740 ps
T341	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3800247195			Jun 28 08:20:00 PM PDT 24	Jun 28 08:24:38 PM PDT 24	3066392974 ps
T877	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.598628676			Jun 28 08:03:55 PM PDT 24	Jun 28 08:17:30 PM PDT 24	9927926040 ps
T430	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3321980314			Jun 28 08:31:31 PM PDT 24	Jun 28 08:38:37 PM PDT 24	3494869800 ps
T878	/workspace/coverage/default/2.chip_sw_aes_smoketest.3682422836			Jun 28 08:22:44 PM PDT 24	Jun 28 08:26:30 PM PDT 24	2826308392 ps
T879	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3398011201			Jun 28 08:28:01 PM PDT 24	Jun 28 08:37:59 PM PDT 24	3905512388 ps
T153	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1252153652			Jun 28 08:05:04 PM PDT 24	Jun 28 08:44:39 PM PDT 24	13011869380 ps
T631	/workspace/coverage/default/1.chip_sw_aes_masking_off.2134670741			Jun 28 08:09:16 PM PDT 24	Jun 28 08:16:17 PM PDT 24	3047179414 ps
T880	/workspace/coverage/default/1.chip_sw_kmac_smoketest.2956578424			Jun 28 08:12:44 PM PDT 24	Jun 28 08:17:39 PM PDT 24	2428219460 ps
T429	/workspace/coverage/default/0.chip_sw_flash_crash_alert.73278555			Jun 28 08:07:22 PM PDT 24	Jun 28 08:19:43 PM PDT 24	6299903956 ps
T81	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1839226104			Jun 28 08:05:50 PM PDT 24	Jun 28 08:11:28 PM PDT 24	3033626496 ps
T145	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.4200589009			Jun 28 08:05:47 PM PDT 24	Jun 28 10:55:53 PM PDT 24	58075515272 ps
T881	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.4097244843			Jun 28 08:29:04 PM PDT 24	Jun 28 09:28:42 PM PDT 24	15287426392 ps
T211	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3285235432			Jun 28 08:18:24 PM PDT 24	Jun 28 08:40:13 PM PDT 24	8010360144 ps
T882	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1737784142			Jun 28 08:11:03 PM PDT 24	Jun 28 08:30:21 PM PDT 24	7233089606 ps
T883	/workspace/coverage/default/0.rom_e2e_asm_init_prod.1217911708			Jun 28 08:05:49 PM PDT 24	Jun 28 09:20:38 PM PDT 24	15808315960 ps
T884	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1423043848			Jun 28 07:59:22 PM PDT 24	Jun 28 08:09:02 PM PDT 24	4296470896 ps
T885	/workspace/coverage/default/2.chip_sw_example_manufacturer.2378237950			Jun 28 08:14:34 PM PDT 24	Jun 28 08:17:48 PM PDT 24	2676707172 ps
T886	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.123086582			Jun 28 08:25:20 PM PDT 24	Jun 28 08:32:14 PM PDT 24	5855098285 ps
T367	/workspace/coverage/default/73.chip_sw_all_escalation_resets.4231865711			Jun 28 08:30:17 PM PDT 24	Jun 28 08:39:45 PM PDT 24	5035740840 ps
T887	/workspace/coverage/default/1.chip_sw_example_flash.3003715266			Jun 28 08:04:12 PM PDT 24	Jun 28 08:09:24 PM PDT 24	3567689404 ps
T511	/workspace/coverage/default/36.chip_sw_all_escalation_resets.2222365653			Jun 28 08:27:55 PM PDT 24	Jun 28 08:40:11 PM PDT 24	5564814636 ps
T357	/workspace/coverage/default/87.chip_sw_all_escalation_resets.574391645			Jun 28 08:32:23 PM PDT 24	Jun 28 08:43:31 PM PDT 24	5361205570 ps
T512	/workspace/coverage/default/32.chip_sw_all_escalation_resets.2600932671			Jun 28 08:28:37 PM PDT 24	Jun 28 08:41:08 PM PDT 24	6608753204 ps
T275	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1039085738			Jun 28 08:18:42 PM PDT 24	Jun 28 08:28:35 PM PDT 24	3759721180 ps
T109	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2747899893			Jun 28 08:02:48 PM PDT 24	Jun 28 08:48:04 PM PDT 24	16404045446 ps
T888	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.537848380			Jun 28 08:27:59 PM PDT 24	Jun 28 08:37:17 PM PDT 24	7106557905 ps
T335	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1831505113			Jun 28 08:01:47 PM PDT 24	Jun 28 08:09:05 PM PDT 24	4485461780 ps
T666	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.981112506			Jun 28 08:25:43 PM PDT 24	Jun 28 08:33:54 PM PDT 24	4333622320 ps
T889	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2853203939			Jun 28 08:20:04 PM PDT 24	Jun 28 09:21:15 PM PDT 24	14479880640 ps
T384	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2394880458			Jun 28 08:01:41 PM PDT 24	Jun 28 08:05:27 PM PDT 24	2745237780 ps
T254	/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2450307575			Jun 28 08:02:54 PM PDT 24	Jun 28 08:45:02 PM PDT 24	27776680461 ps
T890	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2606631208			Jun 28 08:25:46 PM PDT 24	Jun 28 08:40:21 PM PDT 24	11960146892 ps
T382	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3162433270			Jun 28 08:14:27 PM PDT 24	Jun 28 10:01:35 PM PDT 24	24418178460 ps
T891	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.635712215			Jun 28 08:26:26 PM PDT 24	Jun 28 08:29:33 PM PDT 24	2469372464 ps
T250	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1280975890			Jun 28 08:03:36 PM PDT 24	Jun 28 08:09:11 PM PDT 24	3114761012 ps
T82	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.1732494869			Jun 28 08:07:14 PM PDT 24	Jun 28 08:12:39 PM PDT 24	3061061030 ps
T31	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1647424547			Jun 28 08:04:40 PM PDT 24	Jun 28 08:42:52 PM PDT 24	24141462536 ps
T383	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3342362669			Jun 28 08:14:27 PM PDT 24	Jun 28 10:14:48 PM PDT 24	23342299916 ps
T431	/workspace/coverage/default/2.chip_sw_kmac_entropy.3814545633			Jun 28 08:17:35 PM PDT 24	Jun 28 08:21:55 PM PDT 24	2976952830 ps
T63	/workspace/coverage/default/0.chip_tap_straps_testunlock0.1533474401			Jun 28 08:01:13 PM PDT 24	Jun 28 08:03:24 PM PDT 24	2326217031 ps
T29	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.4216811107			Jun 28 08:23:53 PM PDT 24	Jun 28 08:34:56 PM PDT 24	4029479620 ps
T310	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3701880901			Jun 28 08:38:18 PM PDT 24	Jun 28 08:44:33 PM PDT 24	3663418230 ps
T349	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3766974286			Jun 28 08:19:00 PM PDT 24	Jun 28 08:26:47 PM PDT 24	18977531204 ps
T892	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.65574434			Jun 28 08:07:15 PM PDT 24	Jun 28 08:17:12 PM PDT 24	4622562700 ps
T178	/workspace/coverage/default/2.chip_sw_power_sleep_load.4112228126			Jun 28 08:24:49 PM PDT 24	Jun 28 08:32:58 PM PDT 24	4132689280 ps
T701	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2123824733			Jun 28 08:30:47 PM PDT 24	Jun 28 08:41:08 PM PDT 24	4348398776 ps
T893	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3294803578			Jun 28 08:14:52 PM PDT 24	Jun 28 08:18:17 PM PDT 24	3208561916 ps
T894	/workspace/coverage/default/0.chip_sw_hmac_oneshot.758445547			Jun 28 08:00:51 PM PDT 24	Jun 28 08:05:34 PM PDT 24	2803865748 ps
T316	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.484305035			Jun 28 08:26:46 PM PDT 24	Jun 28 08:39:22 PM PDT 24	4125664640 ps
T32	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.109383771			Jun 28 08:18:01 PM PDT 24	Jun 28 09:21:42 PM PDT 24	20940612066 ps
T716	/workspace/coverage/default/95.chip_sw_all_escalation_resets.187209572			Jun 28 08:32:32 PM PDT 24	Jun 28 08:47:44 PM PDT 24	5638400348 ps
T386	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2378126032			Jun 28 08:06:31 PM PDT 24	Jun 28 08:14:15 PM PDT 24	5209292356 ps
T258	/workspace/coverage/default/30.chip_sw_all_escalation_resets.692535470			Jun 28 08:30:21 PM PDT 24	Jun 28 08:40:35 PM PDT 24	5068343688 ps
T895	/workspace/coverage/default/1.chip_sw_csrng_kat_test.1848808591			Jun 28 08:07:09 PM PDT 24	Jun 28 08:12:04 PM PDT 24	2942269492 ps
T896	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1950908349			Jun 28 08:02:03 PM PDT 24	Jun 28 08:04:59 PM PDT 24	2845229270 ps
T49	/workspace/coverage/default/2.chip_sw_spi_device_tpm.2747084058			Jun 28 08:16:00 PM PDT 24	Jun 28 08:22:28 PM PDT 24	3863420947 ps
T78	/workspace/coverage/default/2.chip_jtag_csr_rw.2828157847			Jun 28 08:13:34 PM PDT 24	Jun 28 08:40:21 PM PDT 24	12545935714 ps
T897	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2532801367			Jun 28 08:12:57 PM PDT 24	Jun 28 08:19:15 PM PDT 24	2593180816 ps
T214	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.307900424			Jun 28 08:18:35 PM PDT 24	Jun 28 08:29:38 PM PDT 24	6076128652 ps
T358	/workspace/coverage/default/2.chip_sw_all_escalation_resets.4266134108			Jun 28 08:16:27 PM PDT 24	Jun 28 08:30:57 PM PDT 24	4971149824 ps
T387	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.424460981			Jun 28 08:08:26 PM PDT 24	Jun 28 08:16:46 PM PDT 24	4070791792 ps
T170	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4141305799			Jun 28 08:08:29 PM PDT 24	Jun 28 08:22:38 PM PDT 24	5598700464 ps
T207	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3499121829			Jun 28 08:05:47 PM PDT 24	Jun 28 08:15:52 PM PDT 24	4358786846 ps
T898	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3899857690			Jun 28 08:06:40 PM PDT 24	Jun 28 08:13:33 PM PDT 24	5036367598 ps
T899	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3431473927			Jun 28 08:13:12 PM PDT 24	Jun 28 08:18:09 PM PDT 24	3207697560 ps
T327	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.825110351			Jun 28 08:05:53 PM PDT 24	Jun 28 08:17:55 PM PDT 24	4588397030 ps
T682	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3218262528			Jun 28 08:30:22 PM PDT 24	Jun 28 08:39:17 PM PDT 24	4324030440 ps
T34	/workspace/coverage/default/0.chip_sw_usbdev_stream.2511944633			Jun 28 08:01:04 PM PDT 24	Jun 28 09:12:35 PM PDT 24	18302150334 ps
T900	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1770556212			Jun 28 08:14:43 PM PDT 24	Jun 28 09:26:15 PM PDT 24	15551561528 ps
T901	/workspace/coverage/default/0.chip_sw_aes_idle.405675813			Jun 28 08:05:11 PM PDT 24	Jun 28 08:09:14 PM PDT 24	3397711068 ps
T902	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1105077114			Jun 28 08:01:15 PM PDT 24	Jun 28 08:08:02 PM PDT 24	3157762936 ps
T903	/workspace/coverage/default/2.chip_sw_csrng_smoketest.201515656			Jun 28 08:23:08 PM PDT 24	Jun 28 08:28:37 PM PDT 24	3014648266 ps
T904	/workspace/coverage/default/1.rom_e2e_smoke.630341464			Jun 28 08:15:15 PM PDT 24	Jun 28 09:14:43 PM PDT 24	15394784468 ps
T905	/workspace/coverage/default/0.rom_e2e_asm_init_dev.3166908422			Jun 28 08:06:04 PM PDT 24	Jun 28 09:28:00 PM PDT 24	15017012295 ps
T753	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3431309850			Jun 28 08:28:10 PM PDT 24	Jun 28 08:36:26 PM PDT 24	4060246056 ps
T154	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1839326564			Jun 28 08:05:44 PM PDT 24	Jun 28 08:13:18 PM PDT 24	4625839082 ps
T906	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2188438140			Jun 28 08:03:29 PM PDT 24	Jun 28 08:47:27 PM PDT 24	22966644952 ps
T907	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4015187290			Jun 28 08:23:45 PM PDT 24	Jun 28 08:35:54 PM PDT 24	4995759778 ps
T213	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.4172787337			Jun 28 08:20:57 PM PDT 24	Jun 28 08:44:11 PM PDT 24	8018963772 ps
T908	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3517680052			Jun 28 08:10:25 PM PDT 24	Jun 28 08:22:10 PM PDT 24	6942191500 ps
T677	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2226626691			Jun 28 08:13:31 PM PDT 24	Jun 28 08:20:19 PM PDT 24	3639937968 ps
T909	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3297986675			Jun 28 08:12:26 PM PDT 24	Jun 28 08:19:37 PM PDT 24	4484176500 ps
T910	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1751143770			Jun 28 08:25:33 PM PDT 24	Jun 28 08:30:08 PM PDT 24	3195572484 ps
T381	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2880847219			Jun 28 08:18:55 PM PDT 24	Jun 28 08:23:41 PM PDT 24	2241715880 ps
T911	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2512474561			Jun 28 08:04:35 PM PDT 24	Jun 28 08:29:32 PM PDT 24	6966509928 ps
T912	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.4264780020			Jun 28 08:20:30 PM PDT 24	Jun 28 08:30:27 PM PDT 24	7057491452 ps
T913	/workspace/coverage/default/2.rom_e2e_static_critical.3528083			Jun 28 08:28:45 PM PDT 24	Jun 28 09:30:01 PM PDT 24	17443210820 ps
T356	/workspace/coverage/default/90.chip_sw_all_escalation_resets.1758816666			Jun 28 08:32:49 PM PDT 24	Jun 28 08:44:46 PM PDT 24	5335563608 ps
T914	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3064125264			Jun 28 08:24:09 PM PDT 24	Jun 28 08:33:07 PM PDT 24	4167899488 ps
T144	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2159129746			Jun 28 08:08:15 PM PDT 24	Jun 28 09:15:36 PM PDT 24	18920957492 ps
T915	/workspace/coverage/default/0.chip_sw_otbn_smoketest.1012246716			Jun 28 08:04:06 PM PDT 24	Jun 28 08:30:17 PM PDT 24	6783865866 ps
T174	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2157322715			Jun 28 08:21:04 PM PDT 24	Jun 28 08:30:27 PM PDT 24	5228078932 ps
T916	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1708564638			Jun 28 08:05:21 PM PDT 24	Jun 28 08:31:56 PM PDT 24	14021092920 ps
T707	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.304262374			Jun 28 08:30:15 PM PDT 24	Jun 28 08:39:16 PM PDT 24	3825831064 ps
T679	/workspace/coverage/default/78.chip_sw_all_escalation_resets.2509815939			Jun 28 08:32:59 PM PDT 24	Jun 28 08:45:48 PM PDT 24	4715168000 ps
T917	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1628558023			Jun 28 08:28:06 PM PDT 24	Jun 28 08:32:21 PM PDT 24	2431540408 ps
T435	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1245547282			Jun 28 08:06:14 PM PDT 24	Jun 28 09:09:28 PM PDT 24	17062255520 ps
T715	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1638372738			Jun 28 08:04:31 PM PDT 24	Jun 28 08:16:01 PM PDT 24	5275446440 ps