Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145615	1			T72	129		T73	4		T74	5
values[2]	9506	1			T72	1		T79	1		T248	1
values[3]	3488	1			T447	1		T537	2		T441	16
values[4]	2045	1			T447	1		T537	2		T441	12
values[5]	1391	1			T447	1		T537	2		T441	19
values[6]	886	1			T447	1		T537	2		T441	13
values[7]	692	1			T447	1		T537	2		T441	9
values[8]	617	1			T447	1		T537	2		T441	4
values[9]	555	1			T447	1		T537	2		T441	13
values[10]	471	1			T447	1		T537	2		T441	7
values[11]	413	1			T447	1		T537	2		T441	4
values[12]	427	1			T447	1		T537	2		T441	7
values[13]	384	1			T447	1		T537	2		T441	9
values[14]	374	1			T447	1		T537	2		T441	4
values[15]	333	1			T447	1		T537	2		T441	3
values[16]	359	1			T447	1		T537	2		T441	8
values[17]	321	1			T447	1		T537	2		T441	5
values[18]	380	1			T447	1		T537	2		T441	10
values[19]	352	1			T447	1		T537	2		T441	5
values[20]	335	1			T447	1		T537	2		T441	6
values[21]	368	1			T447	1		T537	2		T441	4
values[22]	336	1			T447	1		T537	2		T441	5
values[23]	364	1			T447	1		T537	2		T441	10
values[24]	316	1			T447	1		T537	2		T545	8
values[25]	402	1			T447	1		T537	2		T545	13
values[26]	292	1			T447	1		T537	2		T545	18
values[27]	314	1			T447	1		T537	2		T545	21
values[28]	352	1			T447	1		T537	2		T545	15
values[29]	311	1			T447	1		T537	2		T545	9
values[30]	309	1			T447	1		T537	2		T545	7
values[31]	313	1			T447	1		T537	2		T545	8
values[32]	328	1			T447	1		T537	2		T545	3
values[33]	309	1			T447	1		T537	2		T781	2
values[34]	333	1			T447	1		T537	2		T781	2
values[35]	311	1			T447	1		T537	2		T781	2
values[36]	323	1			T447	1		T537	2		T781	2
values[37]	325	1			T447	1		T537	2		T781	2
values[38]	296	1			T447	1		T537	2		T781	2
values[39]	271	1			T447	1		T537	2		T781	2
values[40]	283	1			T447	1		T537	2		T781	2
values[41]	307	1			T447	1		T537	2		T781	2
values[42]	299	1			T447	1		T537	3		T781	2
values[43]	295	1			T447	1		T537	2		T781	2
values[44]	328	1			T447	1		T537	2		T781	2
values[45]	245	1			T447	1		T537	2		T781	2
values[46]	254	1			T447	1		T537	2		T781	2
values[47]	265	1			T447	2		T537	2		T781	2
values[48]	303	1			T447	1		T537	2		T781	2
values[49]	310	1			T447	1		T537	2		T781	2
values[50]	233	1			T447	1		T537	2		T781	2
values[51]	244	1			T447	1		T537	2		T781	2
values[52]	235	1			T447	1		T537	2		T781	2
values[53]	257	1			T447	1		T537	2		T781	2
values[54]	259	1			T447	1		T537	2		T781	2
values[55]	256	1			T447	1		T537	2		T781	3
values[56]	199	1			T447	1		T537	2		T781	2
values[57]	243	1			T447	1		T537	2		T781	2
values[58]	203	1			T447	1		T537	2		T781	2
values[59]	248	1			T447	1		T537	2		T781	2
values[60]	260	1			T447	1		T537	2		T781	2
values[61]	205	1			T447	1		T537	2		T781	2
values[62]	185	1			T447	1		T537	2		T781	2
values[63]	210	1			T447	1		T537	2		T781	2
values[64]	295	1			T447	1		T537	2		T781	2
values[65]	278	1			T447	1		T537	2		T781	2
values[66]	228	1			T447	1		T537	2		T781	2
values[67]	226	1			T447	1		T537	2		T781	2
values[68]	224	1			T447	1		T537	2		T781	2
values[69]	182	1			T447	1		T537	2		T781	2
values[70]	146	1			T447	1		T537	2		T781	2
values[71]	162	1			T447	1		T537	2		T781	2
values[72]	149	1			T447	1		T537	2		T781	2
values[73]	153	1			T447	1		T537	2		T781	2
values[74]	146	1			T447	1		T537	2		T781	2
values[75]	179	1			T447	1		T537	2		T781	2
values[76]	159	1			T447	1		T537	2		T781	2
values[77]	142	1			T447	1		T537	2		T781	2
values[78]	137	1			T447	1		T537	2		T781	2
values[79]	172	1			T447	1		T537	2		T781	2
values[80]	152	1			T447	1		T537	2		T781	2
values[81]	144	1			T447	1		T537	2		T781	2
values[82]	121	1			T447	1		T537	2		T781	2
values[83]	131	1			T447	1		T537	2		T781	2
values[84]	123	1			T447	1		T537	2		T781	2
values[85]	114	1			T447	1		T537	2		T781	2
values[86]	117	1			T447	1		T537	2		T781	2
values[87]	140	1			T447	1		T537	2		T781	2
values[88]	154	1			T447	1		T537	2		T781	2
values[89]	120	1			T447	1		T537	2		T781	2
values[90]	113	1			T447	1		T537	2		T781	2
values[91]	128	1			T447	1		T537	2		T781	3
values[92]	126	1			T447	1		T537	2		T781	4
values[93]	123	1			T447	1		T537	2		T781	2
values[94]	119	1			T447	1		T537	2		T781	6
values[95]	136	1			T447	1		T537	8		T781	2
values[96]	127	1			T447	1		T537	2		T781	3
values[97]	145	1			T447	1		T537	3		T781	5
values[98]	108	1			T447	1		T537	2		T781	6
values[99]	133	1			T447	1		T537	4		T781	14
values[100]	118	1			T447	1		T537	2		T781	5
values[101]	131	1			T447	1		T537	6		T781	4
values[102]	129	1			T447	1		T537	2		T781	10
values[103]	109	1			T447	1		T537	4		T781	4
values[104]	127	1			T447	1		T537	2		T781	3
values[105]	120	1			T447	1		T537	2		T781	3
values[106]	99	1			T447	1		T537	2		T781	2
values[107]	126	1			T447	1		T537	3		T781	6
values[108]	113	1			T447	1		T537	2		T781	5
values[109]	87	1			T447	1		T537	3		T781	3
values[110]	97	1			T447	1		T537	2		T781	4
values[111]	134	1			T447	1		T537	6		T781	5
values[112]	121	1			T447	1		T537	3		T781	3
values[113]	107	1			T447	1		T537	3		T781	6
values[114]	94	1			T447	1		T537	3		T781	3
values[115]	85	1			T447	1		T537	4		T781	3
values[116]	78	1			T447	1		T537	6		T781	7
values[117]	87	1			T447	1		T537	3		T781	11
values[118]	96	1			T447	1		T537	2		T781	5
values[119]	91	1			T447	1		T537	4		T781	2
values[120]	93	1			T447	2		T537	2		T781	5
values[121]	92	1			T447	1		T537	2		T781	5
values[122]	101	1			T447	1		T537	3		T781	6
values[123]	82	1			T447	2		T537	7		T781	5
values[124]	96	1			T447	3		T537	3		T781	3
values[125]	123	1			T447	1		T537	6		T781	3
values[126]	187	1			T447	3		T537	8		T781	7
values[127]	994	1			T447	34		T537	48		T781	56
values[128]	7879	1			T447	388		T537	595		T781	594