Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	144481	1			T72	139		T73	6		T74	8
values[2]	10552	1			T72	3		T79	1		T534	1
values[3]	4566	1			T537	1		T532	1		T441	37
values[4]	2901	1			T537	1		T532	1		T441	14
values[5]	2021	1			T537	1		T532	1		T441	9
values[6]	1427	1			T537	1		T532	1		T441	1
values[7]	1083	1			T537	1		T532	1		T448	8
values[8]	926	1			T537	1		T532	1		T448	12
values[9]	780	1			T537	1		T532	1		T448	13
values[10]	688	1			T537	1		T532	1		T448	7
values[11]	592	1			T537	1		T532	1		T448	10
values[12]	595	1			T537	1		T532	1		T448	5
values[13]	452	1			T537	1		T532	1		T448	2
values[14]	489	1			T537	1		T532	1		T448	2
values[15]	459	1			T537	1		T532	1		T448	8
values[16]	424	1			T537	1		T532	1		T448	4
values[17]	474	1			T537	1		T532	1		T448	9
values[18]	408	1			T537	1		T532	1		T448	3
values[19]	347	1			T537	2		T532	1		T448	4
values[20]	391	1			T537	1		T532	1		T448	3
values[21]	408	1			T537	1		T532	1		T448	3
values[22]	421	1			T537	1		T532	1		T448	4
values[23]	381	1			T537	1		T532	1		T448	2
values[24]	343	1			T537	1		T532	1		T448	5
values[25]	419	1			T537	1		T532	1		T448	3
values[26]	366	1			T537	1		T532	1		T448	7
values[27]	422	1			T537	1		T532	1		T448	8
values[28]	393	1			T537	1		T532	1		T448	7
values[29]	391	1			T537	1		T532	1		T448	10
values[30]	409	1			T537	1		T532	1		T448	7
values[31]	331	1			T537	1		T532	1		T448	5
values[32]	332	1			T537	1		T532	1		T448	3
values[33]	347	1			T537	1		T532	1		T448	3
values[34]	362	1			T537	1		T532	1		T448	4
values[35]	405	1			T537	2		T532	1		T448	4
values[36]	422	1			T537	1		T532	1		T448	3
values[37]	402	1			T537	1		T532	1		T448	5
values[38]	427	1			T537	1		T532	1		T448	6
values[39]	392	1			T537	1		T532	1		T448	3
values[40]	364	1			T537	1		T532	1		T448	5
values[41]	314	1			T537	1		T532	1		T448	6
values[42]	334	1			T537	1		T532	1		T448	10
values[43]	363	1			T537	1		T532	2		T448	4
values[44]	343	1			T537	1		T532	1		T448	2
values[45]	300	1			T537	1		T532	1		T448	3
values[46]	293	1			T537	1		T532	1		T448	8
values[47]	318	1			T537	1		T532	1		T448	6
values[48]	319	1			T537	1		T532	1		T448	3
values[49]	309	1			T537	1		T532	1		T448	5
values[50]	329	1			T537	1		T532	1		T448	3
values[51]	306	1			T537	1		T532	1		T448	5
values[52]	286	1			T537	1		T532	1		T448	11
values[53]	274	1			T537	1		T532	1		T448	9
values[54]	296	1			T537	1		T532	1		T448	9
values[55]	305	1			T537	1		T532	1		T448	12
values[56]	232	1			T537	1		T532	1		T448	4
values[57]	228	1			T537	1		T532	1		T448	3
values[58]	270	1			T537	1		T532	1		T448	5
values[59]	239	1			T537	1		T532	1		T448	5
values[60]	258	1			T537	1		T532	1		T448	11
values[61]	228	1			T537	1		T532	1		T448	5
values[62]	214	1			T537	1		T532	1		T448	4
values[63]	246	1			T537	1		T532	1		T448	8
values[64]	215	1			T537	1		T532	1		T448	5
values[65]	298	1			T537	1		T532	1		T448	10
values[66]	259	1			T537	1		T532	1		T448	6
values[67]	232	1			T537	1		T532	2		T448	5
values[68]	210	1			T537	1		T532	1		T448	11
values[69]	207	1			T537	1		T532	1		T448	12
values[70]	195	1			T537	1		T532	1		T448	5
values[71]	195	1			T537	1		T532	1		T448	2
values[72]	171	1			T537	1		T532	1		T448	2
values[73]	145	1			T537	1		T532	1		T448	10
values[74]	148	1			T537	1		T532	1		T448	3
values[75]	148	1			T537	1		T532	1		T448	5
values[76]	143	1			T537	6		T532	1		T448	11
values[77]	135	1			T537	5		T532	1		T448	9
values[78]	112	1			T537	1		T532	1		T448	6
values[79]	109	1			T537	4		T532	1		T448	6
values[80]	95	1			T537	6		T532	1		T448	5
values[81]	103	1			T537	7		T532	1		T448	6
values[82]	102	1			T537	1		T532	1		T448	2
values[83]	130	1			T537	3		T532	1		T448	6
values[84]	128	1			T537	1		T532	1		T448	9
values[85]	122	1			T537	1		T532	3		T448	17
values[86]	106	1			T537	2		T532	3		T448	21
values[87]	110	1			T537	2		T532	9		T448	7
values[88]	135	1			T537	2		T532	10		T448	9
values[89]	130	1			T537	1		T532	5		T448	4
values[90]	105	1			T537	1		T532	1		T448	4
values[91]	102	1			T537	1		T532	1		T448	11
values[92]	96	1			T537	5		T532	3		T448	12
values[93]	111	1			T537	8		T532	3		T448	10
values[94]	125	1			T537	8		T532	2		T448	6
values[95]	130	1			T537	3		T532	1		T448	2
values[96]	107	1			T537	2		T532	1		T448	4
values[97]	141	1			T537	6		T532	3		T448	8
values[98]	102	1			T537	3		T532	4		T448	1
values[99]	112	1			T537	2		T532	2		T448	9
values[100]	132	1			T537	1		T532	3		T448	11
values[101]	103	1			T537	1		T532	5		T448	5
values[102]	107	1			T537	1		T532	4		T448	6
values[103]	107	1			T537	1		T532	3		T448	3
values[104]	100	1			T537	1		T532	4		T448	3
values[105]	102	1			T537	2		T532	4		T448	3
values[106]	103	1			T537	2		T532	2		T448	2
values[107]	96	1			T537	2		T532	2		T448	3
values[108]	101	1			T537	1		T532	1		T448	3
values[109]	94	1			T537	4		T532	1		T448	5
values[110]	79	1			T537	1		T532	1		T448	3
values[111]	72	1			T537	1		T532	1		T448	3
values[112]	79	1			T537	2		T532	3		T448	2
values[113]	104	1			T537	1		T532	2		T448	4
values[114]	110	1			T537	2		T532	3		T448	1
values[115]	93	1			T537	4		T532	5		T448	3
values[116]	100	1			T537	2		T532	5		T448	1
values[117]	76	1			T537	2		T532	1		T448	3
values[118]	80	1			T537	2		T532	1		T448	3
values[119]	88	1			T537	1		T532	1		T448	3
values[120]	91	1			T537	3		T532	6		T448	2
values[121]	74	1			T537	1		T532	1		T448	1
values[122]	80	1			T537	2		T532	3		T448	5
values[123]	67	1			T537	1		T532	1		T448	1
values[124]	89	1			T537	1		T532	1		T448	6
values[125]	136	1			T537	2		T532	1		T448	14
values[126]	192	1			T537	1		T532	2		T448	22
values[127]	962	1			T537	32		T532	32		T448	28
values[128]	7156	1			T537	278		T532	279		T448	7