Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	157544	1			T72	99		T73	4		T74	6
values[2]	4368	1			T73	1		T534	1		T491	4
values[3]	2165	1			T532	1		T585	22		T579	1
values[4]	1445	1			T532	1		T585	13		T583	57
values[5]	1222	1			T532	1		T585	9		T583	61
values[6]	986	1			T532	1		T585	11		T583	45
values[7]	833	1			T532	1		T585	9		T583	48
values[8]	748	1			T532	1		T585	12		T583	41
values[9]	686	1			T532	1		T585	18		T583	25
values[10]	626	1			T532	1		T585	13		T583	21
values[11]	580	1			T532	1		T585	2		T583	8
values[12]	535	1			T532	1		T583	10		T449	5
values[13]	468	1			T532	1		T583	5		T449	3
values[14]	412	1			T532	1		T583	13		T449	1
values[15]	430	1			T532	1		T583	4		T449	9
values[16]	394	1			T532	1		T583	3		T449	13
values[17]	373	1			T532	1		T583	1		T449	24
values[18]	376	1			T532	1		T449	38		T782	1
values[19]	358	1			T532	1		T449	26		T782	1
values[20]	306	1			T532	1		T449	22		T782	1
values[21]	265	1			T532	1		T449	26		T782	1
values[22]	241	1			T532	1		T449	24		T782	1
values[23]	201	1			T532	1		T449	9		T782	1
values[24]	198	1			T532	1		T449	7		T782	1
values[25]	222	1			T532	1		T449	10		T782	1
values[26]	199	1			T532	1		T449	8		T782	1
values[27]	206	1			T532	1		T449	7		T782	1
values[28]	259	1			T532	1		T449	39		T782	1
values[29]	225	1			T532	1		T449	35		T782	1
values[30]	225	1			T532	1		T449	39		T782	1
values[31]	192	1			T532	1		T449	26		T782	1
values[32]	166	1			T532	1		T449	5		T782	1
values[33]	164	1			T532	1		T782	1		T802	5
values[34]	134	1			T532	1		T782	1		T802	3
values[35]	141	1			T532	1		T782	1		T802	1
values[36]	136	1			T532	1		T782	1		T802	5
values[37]	120	1			T532	1		T782	1		T802	1
values[38]	105	1			T532	1		T782	1		T802	6
values[39]	84	1			T532	1		T782	1		T802	8
values[40]	77	1			T532	1		T782	1		T802	6
values[41]	87	1			T532	1		T782	1		T802	6
values[42]	74	1			T532	1		T782	1		T802	1
values[43]	81	1			T532	1		T782	1		T802	4
values[44]	88	1			T532	1		T782	1		T802	1
values[45]	72	1			T532	1		T782	1		T802	3
values[46]	76	1			T532	1		T782	1		T802	7
values[47]	61	1			T532	1		T782	1		T802	5
values[48]	66	1			T532	1		T782	1		T802	3
values[49]	66	1			T532	1		T782	1		T802	4
values[50]	62	1			T532	1		T782	1		T802	2
values[51]	66	1			T532	1		T782	1		T802	2
values[52]	78	1			T532	1		T782	1		T802	4
values[53]	87	1			T532	1		T782	1		T802	7
values[54]	95	1			T532	1		T782	1		T802	1
values[55]	76	1			T532	1		T782	1		T802	1
values[56]	78	1			T532	1		T782	1		T802	1
values[57]	63	1			T532	1		T782	1		T802	1
values[58]	78	1			T532	1		T782	1		T802	4
values[59]	80	1			T532	1		T782	1		T802	8
values[60]	66	1			T532	1		T782	1		T802	4
values[61]	86	1			T532	1		T782	1		T802	5
values[62]	74	1			T532	1		T782	1		T802	2
values[63]	49	1			T532	1		T782	1		T802	1
values[64]	63	1			T532	1		T782	1		T802	5
values[65]	56	1			T532	1		T782	1		T802	3
values[66]	45	1			T532	1		T782	1		T802	1
values[67]	52	1			T532	1		T782	1		T802	2
values[68]	52	1			T532	1		T782	1		T802	2
values[69]	61	1			T532	1		T782	1		T802	3
values[70]	54	1			T532	1		T782	1		T802	1
values[71]	55	1			T532	1		T782	1		T802	1
values[72]	59	1			T532	1		T782	1		T802	2
values[73]	57	1			T532	1		T782	1		T802	2
values[74]	69	1			T532	1		T782	1		T802	3
values[75]	66	1			T532	1		T782	1		T802	5
values[76]	56	1			T532	1		T782	1		T802	9
values[77]	65	1			T532	1		T782	1		T802	9
values[78]	69	1			T532	1		T782	1		T802	1
values[79]	68	1			T532	1		T782	1		T802	6
values[80]	57	1			T532	1		T782	1		T802	5
values[81]	68	1			T532	1		T782	1		T802	7
values[82]	75	1			T532	1		T782	1		T802	3
values[83]	72	1			T532	1		T782	1		T802	1
values[84]	81	1			T532	1		T782	1		T802	6
values[85]	70	1			T532	1		T782	1		T802	8
values[86]	70	1			T532	1		T782	1		T802	2
values[87]	85	1			T532	1		T782	1		T802	4
values[88]	84	1			T532	1		T782	1		T802	10
values[89]	68	1			T532	1		T782	1		T802	5
values[90]	71	1			T532	1		T782	1		T802	4
values[91]	71	1			T532	1		T782	1		T802	3
values[92]	87	1			T532	2		T782	1		T802	4
values[93]	73	1			T532	1		T782	1		T802	3
values[94]	80	1			T532	1		T782	1		T802	4
values[95]	104	1			T532	1		T782	1		T802	4
values[96]	79	1			T532	1		T782	1		T802	2
values[97]	97	1			T532	1		T782	1		T802	5
values[98]	92	1			T532	1		T782	1		T802	4
values[99]	98	1			T532	2		T782	1		T802	6
values[100]	85	1			T532	2		T782	1		T802	6
values[101]	82	1			T532	3		T782	2		T802	3
values[102]	75	1			T532	2		T782	1		T802	3
values[103]	76	1			T532	1		T782	2		T802	2
values[104]	82	1			T532	1		T782	6		T802	1
values[105]	85	1			T532	3		T782	2		T802	3
values[106]	100	1			T532	5		T782	2		T802	2
values[107]	89	1			T532	1		T782	8		T802	1
values[108]	104	1			T532	1		T782	3		T802	3
values[109]	111	1			T532	2		T782	5		T802	4
values[110]	83	1			T532	4		T782	4		T802	2
values[111]	83	1			T532	2		T782	4		T802	8
values[112]	83	1			T532	1		T782	4		T802	3
values[113]	105	1			T532	4		T782	8		T802	5
values[114]	116	1			T532	2		T782	1		T802	4
values[115]	114	1			T532	4		T782	2		T802	3
values[116]	117	1			T532	2		T782	1		T802	14
values[117]	126	1			T532	3		T782	8		T802	6
values[118]	103	1			T532	1		T782	2		T802	2
values[119]	97	1			T532	1		T782	1		T802	3
values[120]	97	1			T532	3		T782	1		T802	4
values[121]	102	1			T532	1		T782	1		T802	5
values[122]	132	1			T532	1		T782	2		T802	2
values[123]	139	1			T532	4		T782	1		T802	6
values[124]	170	1			T532	1		T782	2		T802	4
values[125]	345	1			T532	2		T782	3		T802	8
values[126]	758	1			T532	26		T782	10		T802	14
values[127]	2752	1			T532	140		T782	88		T802	12
values[128]	5045	1			T532	210		T782	194		T803	285