Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	467	1			T80	2		T489	5		T447	1
all_values[1]	452	1			T247	2		T489	2		T537	1
all_values[2]	448	1			T247	3		T489	1		T447	1
all_values[3]	439	1			T247	1		T489	3		T585	2
all_values[4]	463	1			T247	2		T489	2		T539	2
all_values[5]	461	1			T80	2		T247	2		T489	2
all_values[6]	503	1			T80	2		T247	2		T248	1
all_values[7]	465	1			T80	1		T247	1		T489	2
all_values[8]	490	1			T489	3		T537	1		T539	1
all_values[9]	480	1			T80	2		T489	1		T452	1
all_values[10]	495	1			T80	2		T247	1		T489	5
all_values[11]	465	1			T247	1		T248	1		T539	1
all_values[12]	458	1			T80	1		T247	2		T489	4
all_values[13]	472	1			T80	2		T489	2		T548	1
all_values[14]	440	1			T247	1		T248	1		T489	4
all_values[15]	484	1			T72	1		T80	1		T247	1
all_values[16]	459	1			T247	2		T489	2		T447	1
all_values[17]	493	1			T80	1		T247	1		T489	3
all_values[18]	441	1			T80	2		T247	2		T248	1
all_values[19]	514	1			T247	2		T248	1		T489	4
all_values[20]	472	1			T247	1		T447	1		T452	2
all_values[21]	518	1			T247	2		T489	3		T516	1
all_values[22]	505	1			T247	4		T248	1		T725	1
all_values[23]	489	1			T80	1		T447	2		T452	1
all_values[24]	491	1			T80	1		T247	5		T489	4
all_values[25]	515	1			T80	2		T247	3		T489	1
all_values[26]	438	1			T80	2		T247	3		T441	1
all_values[27]	463	1			T489	3		T452	1		T516	2
all_values[28]	482	1			T247	6		T489	2		T447	1
all_values[29]	457	1			T80	1		T247	2		T489	4
all_values[30]	472	1			T247	2		T489	3		T452	1
all_values[31]	481	1			T247	3		T489	2		T441	1
all_values[32]	491	1			T80	1		T247	4		T489	2
all_values[33]	469	1			T489	1		T447	1		T537	2
all_values[34]	526	1			T489	3		T537	1		T441	1
all_values[35]	503	1			T80	1		T247	4		T248	1
all_values[36]	462	1			T80	2		T725	1		T489	2
all_values[37]	472	1			T72	1		T80	1		T489	4
all_values[38]	487	1			T247	4		T489	2		T447	1
all_values[39]	490	1			T247	2		T489	2		T532	1
all_values[40]	466	1			T80	1		T247	1		T248	1
all_values[41]	487	1			T247	3		T725	1		T489	1
all_values[42]	475	1			T247	2		T489	2		T585	4
all_values[43]	461	1			T247	1		T489	5		T516	1
all_values[44]	482	1			T80	1		T247	1		T489	2
all_values[45]	488	1			T80	2		T489	1		T537	1
all_values[46]	475	1			T247	4		T489	1		T447	1
all_values[47]	494	1			T80	3		T489	2		T532	1
all_values[48]	446	1			T247	2		T489	2		T447	1
all_values[49]	495	1			T72	1		T247	2		T489	3