Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3627	1			T72	1		T80	4		T247	24
all_values[1]	3541	1			T72	2		T80	5		T247	20
all_values[2]	3498	1			T80	2		T247	21		T248	5
all_values[3]	3678	1			T72	2		T80	2		T247	30
all_values[4]	3579	1			T80	3		T247	15		T248	2
all_values[5]	3553	1			T72	1		T80	4		T247	23
all_values[6]	3595	1			T72	1		T80	8		T247	20
all_values[7]	3590	1			T72	4		T80	2		T247	17
all_values[8]	3707	1			T72	2		T80	3		T247	20
all_values[9]	3650	1			T80	2		T247	23		T248	4
all_values[10]	3690	1			T72	1		T80	2		T247	14
all_values[11]	3711	1			T72	1		T80	4		T247	26
all_values[12]	3585	1			T80	5		T247	18		T248	5
all_values[13]	3638	1			T72	3		T80	3		T247	16
all_values[14]	3570	1			T72	1		T80	4		T247	22
all_values[15]	3702	1			T72	4		T80	3		T247	28
all_values[16]	3692	1			T72	1		T80	2		T247	25
all_values[17]	3605	1			T80	2		T247	19		T248	2
all_values[18]	3563	1			T72	3		T80	6		T247	20
all_values[19]	3553	1			T72	1		T80	6		T247	21
all_values[20]	3591	1			T80	2		T247	23		T248	6
all_values[21]	3565	1			T72	1		T80	2		T247	25
all_values[22]	3538	1			T80	4		T247	20		T248	5
all_values[23]	3651	1			T72	3		T80	7		T247	20
all_values[24]	3675	1			T72	3		T80	5		T247	26
all_values[25]	3619	1			T72	1		T80	9		T247	13
all_values[26]	3879	1			T80	5		T247	22		T248	6
all_values[27]	3560	1			T72	2		T80	6		T247	20
all_values[28]	3665	1			T72	2		T80	5		T247	16
all_values[29]	3643	1			T80	5		T247	25		T248	4
all_values[30]	3621	1			T72	1		T80	5		T247	20
all_values[31]	3599	1			T72	3		T247	22		T248	2
all_values[32]	3551	1			T72	1		T80	4		T247	28
all_values[33]	3816	1			T72	2		T80	4		T247	20
all_values[34]	3643	1			T72	1		T80	5		T247	19
all_values[35]	3580	1			T80	7		T247	19		T248	5
all_values[36]	3606	1			T72	2		T80	5		T247	20
all_values[37]	3589	1			T72	1		T80	2		T247	29
all_values[38]	3606	1			T72	2		T80	5		T247	18
all_values[39]	3611	1			T72	1		T80	3		T247	19
all_values[40]	3606	1			T72	1		T80	4		T247	11
all_values[41]	3560	1			T72	1		T80	4		T247	27
all_values[42]	3625	1			T72	1		T80	3		T247	13
all_values[43]	3670	1			T72	1		T80	5		T247	21
all_values[44]	3636	1			T72	2		T80	2		T247	22
all_values[45]	3668	1			T80	6		T247	31		T248	10
all_values[46]	3558	1			T80	6		T247	21		T248	3
all_values[47]	3592	1			T72	1		T80	5		T247	21
all_values[48]	3569	1			T80	5		T247	24		T248	8
all_values[49]	3651	1			T80	3		T247	20		T248	6
all_values[50]	3615	1			T80	4		T247	18		T248	6
all_values[51]	3631	1			T80	2		T247	26		T248	4
all_values[52]	3650	1			T80	2		T247	14		T248	5
all_values[53]	3627	1			T72	4		T80	5		T247	26
all_values[54]	3609	1			T72	2		T80	4		T247	19
all_values[55]	3660	1			T72	3		T80	5		T247	23
all_values[56]	3603	1			T72	2		T80	2		T247	25
all_values[57]	3611	1			T72	3		T80	4		T247	22
all_values[58]	3667	1			T80	2		T247	30		T248	4
all_values[59]	3586	1			T80	3		T247	29		T248	3
all_values[60]	3591	1			T72	3		T80	5		T247	20
all_values[61]	3543	1			T72	3		T80	2		T247	27
all_values[62]	3672	1			T72	1		T80	3		T247	18
all_values[63]	3684	1			T80	5		T247	22		T248	4