Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	194639	1			T73	113		T74	4		T75	8
values[2]	5494	1			T74	1		T117	2		T226	5
values[3]	2616	1			T420	39		T519	48		T524	2
values[4]	1949	1			T420	27		T519	53		T524	1
values[5]	1546	1			T420	72		T519	15		T524	4
values[6]	1249	1			T420	62		T519	5		T524	3
values[7]	1074	1			T420	32		T519	3		T524	3
values[8]	931	1			T420	15		T519	5		T524	1
values[9]	777	1			T420	12		T519	10		T524	2
values[10]	597	1			T420	10		T519	8		T524	4
values[11]	626	1			T420	12		T519	8		T524	1
values[12]	611	1			T420	5		T519	22		T524	1
values[13]	583	1			T420	9		T519	30		T524	2
values[14]	472	1			T420	4		T519	18		T524	2
values[15]	488	1			T420	5		T519	20		T524	6
values[16]	445	1			T420	2		T519	38		T524	3
values[17]	442	1			T519	42		T524	1		T775	1
values[18]	389	1			T519	56		T524	2		T775	1
values[19]	353	1			T519	48		T524	8		T775	1
values[20]	315	1			T519	37		T524	2		T775	1
values[21]	323	1			T519	18		T524	2		T775	1
values[22]	252	1			T519	9		T524	3		T775	1
values[23]	219	1			T519	9		T524	1		T775	1
values[24]	169	1			T519	1		T524	4		T775	1
values[25]	136	1			T524	4		T775	1		T486	2
values[26]	140	1			T524	3		T775	1		T486	3
values[27]	137	1			T524	3		T775	1		T486	4
values[28]	143	1			T524	6		T775	1		T486	9
values[29]	111	1			T524	3		T775	1		T486	18
values[30]	94	1			T524	3		T775	1		T486	10
values[31]	55	1			T524	1		T775	1		T486	5
values[32]	53	1			T524	2		T775	1		T486	8
values[33]	59	1			T524	2		T775	1		T486	16
values[34]	63	1			T524	2		T775	1		T486	22
values[35]	78	1			T524	3		T775	1		T486	34
values[36]	99	1			T524	7		T775	1		T486	46
values[37]	61	1			T524	3		T775	1		T486	20
values[38]	67	1			T524	6		T775	1		T486	17
values[39]	53	1			T524	2		T775	1		T486	13
values[40]	48	1			T524	3		T775	1		T486	10
values[41]	36	1			T524	3		T775	1		T486	4
values[42]	32	1			T524	4		T775	2		T486	1
values[43]	36	1			T524	2		T775	1		T486	5
values[44]	39	1			T524	2		T775	1		T486	7
values[45]	43	1			T524	2		T775	1		T486	3
values[46]	40	1			T524	2		T775	1		T486	5
values[47]	41	1			T524	2		T775	1		T486	8
values[48]	50	1			T524	4		T775	1		T486	14
values[49]	49	1			T524	1		T775	1		T486	16
values[50]	45	1			T524	5		T775	1		T486	10
values[51]	48	1			T524	2		T775	1		T486	13
values[52]	37	1			T524	2		T775	1		T486	4
values[53]	40	1			T524	9		T775	1		T486	1
values[54]	39	1			T524	8		T775	1		T486	2
values[55]	36	1			T524	3		T775	1		T486	2
values[56]	47	1			T524	4		T775	1		T486	7
values[57]	60	1			T524	8		T775	1		T486	21
values[58]	48	1			T524	5		T775	1		T486	13
values[59]	42	1			T524	4		T775	1		T486	7
values[60]	36	1			T524	2		T775	1		T486	4
values[61]	31	1			T524	4		T775	1		T585	2
values[62]	33	1			T524	5		T775	1		T585	1
values[63]	47	1			T524	7		T775	1		T585	4
values[64]	31	1			T524	2		T775	1		T585	2
values[65]	31	1			T524	4		T775	1		T585	1
values[66]	34	1			T524	3		T775	1		T585	3
values[67]	31	1			T524	1		T775	1		T585	1
values[68]	33	1			T524	3		T775	1		T585	2
values[69]	36	1			T524	2		T775	1		T585	5
values[70]	34	1			T524	3		T775	1		T585	5
values[71]	31	1			T524	1		T775	1		T585	4
values[72]	28	1			T524	2		T775	1		T585	1
values[73]	33	1			T524	3		T775	1		T585	1
values[74]	30	1			T524	1		T775	1		T585	3
values[75]	33	1			T524	1		T775	1		T585	1
values[76]	36	1			T524	3		T775	1		T585	1
values[77]	37	1			T524	2		T775	1		T585	3
values[78]	39	1			T524	3		T775	1		T585	2
values[79]	32	1			T524	4		T775	1		T585	1
values[80]	27	1			T524	1		T775	1		T585	1
values[81]	39	1			T524	3		T775	1		T585	1
values[82]	40	1			T524	2		T775	1		T585	6
values[83]	39	1			T524	3		T775	1		T585	6
values[84]	53	1			T524	4		T775	1		T585	8
values[85]	30	1			T524	1		T775	1		T585	1
values[86]	42	1			T524	4		T775	1		T585	1
values[87]	41	1			T524	2		T775	1		T585	3
values[88]	40	1			T524	5		T775	1		T585	1
values[89]	35	1			T524	2		T775	1		T585	2
values[90]	43	1			T524	3		T775	1		T585	5
values[91]	47	1			T524	1		T775	1		T585	1
values[92]	50	1			T524	3		T775	1		T585	5
values[93]	43	1			T524	1		T775	2		T585	7
values[94]	80	1			T524	5		T775	1		T585	8
values[95]	58	1			T524	4		T775	1		T585	3
values[96]	38	1			T524	2		T775	1		T585	2
values[97]	49	1			T524	3		T775	1		T585	2
values[98]	54	1			T524	1		T775	1		T585	3
values[99]	72	1			T524	4		T775	1		T585	6
values[100]	59	1			T524	2		T775	1		T585	3
values[101]	40	1			T524	1		T775	1		T585	3
values[102]	39	1			T524	2		T775	1		T585	1
values[103]	46	1			T524	1		T775	1		T585	4
values[104]	65	1			T524	2		T775	1		T585	2
values[105]	56	1			T524	3		T775	1		T585	6
values[106]	48	1			T524	2		T775	1		T585	2
values[107]	48	1			T524	1		T775	1		T585	4
values[108]	63	1			T524	3		T775	1		T585	5
values[109]	60	1			T524	3		T775	1		T585	1
values[110]	69	1			T524	1		T775	1		T585	1
values[111]	67	1			T524	3		T775	1		T585	4
values[112]	80	1			T524	2		T775	1		T585	6
values[113]	69	1			T524	2		T775	1		T585	5
values[114]	57	1			T524	3		T775	1		T585	3
values[115]	62	1			T524	4		T775	1		T585	3
values[116]	53	1			T524	2		T775	1		T585	5
values[117]	56	1			T524	4		T775	1		T585	5
values[118]	58	1			T524	6		T775	1		T585	6
values[119]	68	1			T524	3		T775	1		T585	2
values[120]	65	1			T524	2		T775	2		T585	5
values[121]	58	1			T524	2		T775	1		T585	1
values[122]	77	1			T524	3		T775	3		T585	10
values[123]	86	1			T524	7		T775	2		T585	6
values[124]	113	1			T524	9		T775	2		T585	3
values[125]	255	1			T524	41		T775	1		T585	28
values[126]	549	1			T524	39		T775	25		T585	29
values[127]	2450	1			T524	16		T775	156		T585	21
values[128]	4260	1			T524	2		T775	275		T585	4