Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.02	95.45	93.64	95.54		94.43	97.53	99.54

Total tests in report: 2884

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.02	40.02	45.63	45.63	44.56	44.56	32.02	32.02			58.95	58.95	58.57	58.57	0.41	0.41	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.877338670
49.77	9.75	51.93	6.30	58.81	14.26	32.69	0.67			69.65	10.70	83.74	25.17	1.79	1.37	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1572878336
55.15	5.38	63.65	11.72	66.25	7.43	35.55	2.87			79.91	10.26	83.74	0.00	1.79	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.2848502594
60.52	5.37	75.00	11.35	68.33	2.08	42.98	7.42			80.44	0.53	83.74	0.00	12.64	10.86	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2069220409
64.56	4.04	75.00	0.00	68.33	0.00	42.98	0.00			80.44	0.00	83.74	0.00	36.91	24.26	/workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.234350832
68.06	3.50	81.08	6.08	72.71	4.38	46.93	3.96			82.46	2.02	88.29	4.55	36.91	0.00	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3755987799
71.00	2.94	81.08	0.00	72.72	0.01	46.93	0.00			82.46	0.00	88.29	0.00	54.52	17.61	/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.986888901
73.61	2.61	81.08	0.00	72.72	0.01	62.22	15.29			82.46	0.00	88.64	0.35	54.52	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1008232664
75.62	2.02	81.08	0.00	72.97	0.25	62.22	0.00			82.54	0.08	88.64	0.00	66.28	11.76	/workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1562959968
77.52	1.90	84.24	3.16	76.53	3.56	63.61	1.39			85.83	3.29	88.64	0.00	66.28	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2195897089
79.19	1.67	84.24	0.00	76.53	0.00	63.61	0.00			85.83	0.00	88.64	0.00	76.32	10.05	/workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1190197186
80.83	1.63	84.36	0.13	76.63	0.10	72.67	9.06			86.00	0.17	88.99	0.35	76.32	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4115525501
82.19	1.36	85.06	0.69	77.53	0.90	76.90	4.23			86.54	0.54	89.16	0.17	77.97	1.64	/workspace/coverage/default/1.chip_sw_alert_test.407874422
83.42	1.23	85.06	0.01	79.46	1.94	77.63	0.73			86.57	0.03	89.16	0.00	82.66	4.69	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1420324854
84.59	1.17	87.01	1.94	81.43	1.97	78.43	0.80			88.86	2.29	89.16	0.00	82.66	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1377640755
85.48	0.89	88.17	1.16	82.36	0.92	78.99	0.55			89.99	1.13	90.73	1.57	82.66	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2419949325
86.33	0.85	88.92	0.75	82.58	0.22	79.00	0.01			90.26	0.28	94.58	3.85	82.66	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1596152227
87.03	0.70	88.92	0.00	82.58	0.00	79.00	0.00			90.26	0.00	94.58	0.00	86.85	4.19	/workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3420153831
87.71	0.68	90.00	1.08	83.14	0.57	80.64	1.64			90.72	0.45	94.93	0.35	86.85	0.00	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3746653523
88.35	0.63	90.01	0.01	86.53	3.39	80.64	0.00			90.72	0.00	94.93	0.00	87.26	0.41	/workspace/coverage/cover_reg_top/22.chip_tl_errors.3730658646
88.98	0.63	90.01	0.00	86.53	0.00	84.41	3.77			90.72	0.00	94.93	0.00	87.26	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1575204411
89.57	0.60	91.29	1.28	87.57	1.04	84.81	0.40			91.58	0.86	94.93	0.00	87.26	0.00	/workspace/coverage/default/0.chip_sw_gpio.1755264002
90.13	0.56	91.33	0.03	87.65	0.08	84.81	0.00			91.59	0.01	94.93	0.00	90.51	3.24	/workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.399440053
90.62	0.48	92.26	0.94	87.88	0.23	85.73	0.92			91.69	0.11	95.63	0.70	90.51	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.4100349205
90.97	0.35	92.79	0.53	88.38	0.50	86.29	0.56			92.20	0.51	95.63	0.00	90.51	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.1677499675
91.31	0.34	93.03	0.24	88.53	0.14	87.15	0.86			92.33	0.13	96.15	0.52	90.67	0.16	/workspace/coverage/default/10.chip_sw_all_escalation_resets.842828985
91.65	0.34	93.03	0.00	88.56	0.04	87.15	0.00			92.33	0.00	96.15	0.00	92.69	2.02	/workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.1953121934
91.96	0.30	93.34	0.31	88.64	0.07	88.51	1.36			92.40	0.06	96.15	0.00	92.69	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.2336238962
92.23	0.27	93.34	0.00	88.74	0.10	88.51	0.00			92.43	0.03	96.15	0.00	94.20	1.50	/workspace/coverage/cover_reg_top/54.xbar_access_same_device.4179437928
92.48	0.25	93.34	0.00	88.74	0.00	88.51	0.00			92.43	0.00	96.15	0.00	95.72	1.53	/workspace/coverage/cover_reg_top/98.xbar_access_same_device.3986349645
92.73	0.25	93.35	0.01	88.91	0.17	88.51	0.00			92.44	0.01	96.15	0.00	97.04	1.32	/workspace/coverage/cover_reg_top/89.xbar_random.2817103595
92.96	0.23	93.36	0.01	88.91	0.01	89.89	1.38			92.44	0.00	96.15	0.00	97.04	0.00	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3471100114
93.14	0.17	93.58	0.22	89.25	0.34	90.06	0.17			92.73	0.29	96.15	0.00	97.05	0.01	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.27594618
93.30	0.16	93.58	0.00	89.25	0.00	91.01	0.96			92.73	0.00	96.15	0.00	97.05	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2840991928
93.44	0.14	93.74	0.17	89.38	0.13	91.11	0.09			92.86	0.13	96.50	0.35	97.05	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2764072366
93.58	0.14	93.95	0.21	89.70	0.32	91.40	0.29			92.86	0.00	96.50	0.00	97.05	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3703906782
93.71	0.14	93.96	0.01	90.08	0.38	91.40	0.00			93.28	0.42	96.50	0.00	97.05	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2242646354
93.84	0.12	93.96	0.00	90.12	0.04	91.40	0.00			93.28	0.00	96.50	0.00	97.74	0.69	/workspace/coverage/cover_reg_top/94.xbar_random_large_delays.3531622157
93.95	0.11	94.01	0.05	90.14	0.02	91.95	0.55			93.31	0.02	96.50	0.00	97.78	0.04	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2269127382
94.06	0.11	94.01	0.00	90.14	0.00	92.59	0.64			93.31	0.00	96.50	0.00	97.78	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.826844577
94.16	0.10	94.01	0.00	90.76	0.63	92.59	0.00			93.31	0.00	96.50	0.00	97.78	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.1004159014
94.26	0.10	94.07	0.06	90.93	0.16	92.64	0.04			93.48	0.17	96.68	0.17	97.78	0.00	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2011761892
94.35	0.09	94.07	0.00	91.17	0.24	92.64	0.00			93.75	0.28	96.68	0.00	97.78	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3358225539
94.43	0.08	94.07	0.00	91.17	0.00	93.15	0.51			93.75	0.00	96.68	0.00	97.78	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1689991033
94.51	0.08	94.07	0.01	91.21	0.04	93.41	0.27			93.76	0.01	96.85	0.17	97.78	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3269340551
94.59	0.07	94.07	0.00	91.38	0.17	93.41	0.00			93.79	0.03	96.85	0.00	98.01	0.23	/workspace/coverage/cover_reg_top/25.xbar_stress_all.201771606
94.66	0.07	94.10	0.03	91.40	0.02	93.58	0.17			93.83	0.03	97.03	0.17	98.01	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3763947448
94.72	0.06	94.17	0.07	91.58	0.18	93.58	0.00			93.96	0.13	97.03	0.00	98.01	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2830015827
94.77	0.05	94.17	0.00	91.74	0.16	93.58	0.00			93.99	0.03	97.03	0.00	98.12	0.11	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1658999166
94.82	0.05	94.17	0.00	91.74	0.00	93.87	0.29			93.99	0.00	97.03	0.00	98.12	0.00	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4041345422
94.87	0.05	94.20	0.03	91.77	0.03	93.88	0.01			94.02	0.03	97.20	0.17	98.13	0.01	/workspace/coverage/default/69.chip_sw_all_escalation_resets.2484131590
94.91	0.04	94.23	0.03	91.77	0.01	94.11	0.23			94.02	0.00	97.20	0.00	98.13	0.00	/workspace/coverage/cover_reg_top/47.xbar_same_source.1072863604
94.95	0.04	94.24	0.01	91.79	0.01	94.11	0.00			94.04	0.02	97.38	0.17	98.14	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1778876384
94.99	0.04	94.24	0.00	91.79	0.00	94.34	0.23			94.04	0.00	97.38	0.00	98.14	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3777306395
95.03	0.04	94.24	0.00	91.83	0.04	94.34	0.00			94.04	0.00	97.38	0.00	98.33	0.19	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2592524947
95.06	0.04	94.24	0.01	91.85	0.01	94.34	0.00			94.05	0.01	97.55	0.17	98.34	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.702091528
95.10	0.04	94.26	0.01	92.04	0.20	94.34	0.00			94.05	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2534292579
95.13	0.03	94.26	0.00	92.04	0.00	94.55	0.21			94.05	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3792304859
95.16	0.03	94.28	0.02	92.11	0.07	94.60	0.05			94.10	0.05	97.55	0.00	98.34	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2320381896
95.20	0.03	94.28	0.00	92.30	0.19	94.60	0.00			94.10	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.2637419077
95.23	0.03	94.35	0.07	92.30	0.00	94.71	0.11			94.11	0.01	97.55	0.00	98.34	0.00	/workspace/coverage/default/1.chip_tap_straps_testunlock0.3761482226
95.26	0.03	94.42	0.07	92.33	0.03	94.73	0.01			94.16	0.05	97.55	0.00	98.34	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.371059492
95.28	0.03	94.48	0.06	92.38	0.05	94.73	0.01			94.21	0.05	97.55	0.00	98.34	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.615944440
95.31	0.02	94.55	0.07	92.43	0.05	94.73	0.00			94.24	0.03	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.220624408
95.33	0.02	94.55	0.00	92.57	0.14	94.73	0.00			94.24	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.2752682144
95.35	0.02	94.61	0.07	92.62	0.05	94.73	0.00			94.26	0.02	97.55	0.00	98.34	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2281748658
95.37	0.02	94.68	0.07	92.67	0.05	94.73	0.00			94.27	0.02	97.55	0.00	98.34	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1694826360
95.39	0.02	94.70	0.02	92.71	0.04	94.73	0.01			94.32	0.05	97.55	0.00	98.36	0.01	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1643255766
95.41	0.02	94.70	0.00	92.71	0.01	94.73	0.00			94.32	0.00	97.55	0.00	98.47	0.12	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.1796963386
95.43	0.02	94.70	0.00	92.83	0.11	94.73	0.00			94.32	0.00	97.55	0.00	98.47	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1331138773
95.45	0.02	94.70	0.00	92.94	0.11	94.73	0.00			94.32	0.00	97.55	0.00	98.47	0.00	/workspace/coverage/cover_reg_top/8.chip_tl_errors.125160156
95.47	0.02	94.70	0.00	92.97	0.03	94.73	0.00			94.34	0.02	97.55	0.00	98.53	0.06	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.4037549441
95.49	0.02	94.70	0.00	92.97	0.00	94.83	0.10			94.34	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2085783097
95.50	0.01	94.70	0.00	92.97	0.00	94.83	0.00			94.34	0.00	97.55	0.00	98.61	0.08	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3316980701
95.51	0.01	94.70	0.00	92.97	0.00	94.91	0.08			94.34	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3348427452
95.53	0.01	94.70	0.00	92.97	0.00	94.99	0.08			94.34	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3770450305
95.54	0.01	94.71	0.01	93.00	0.03	95.01	0.02			94.35	0.02	97.55	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.750717036
95.55	0.01	94.71	0.00	93.00	0.00	95.08	0.07			94.35	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1931104028
95.56	0.01	94.73	0.02	93.02	0.02	95.10	0.02			94.35	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1079276720
95.57	0.01	94.73	0.00	93.08	0.06	95.10	0.00			94.35	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.2970509550
95.58	0.01	94.75	0.02	93.09	0.01	95.11	0.01			94.37	0.02	97.55	0.00	98.61	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2565293332
95.59	0.01	94.77	0.02	93.09	0.01	95.12	0.01			94.39	0.02	97.55	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3709976788
95.60	0.01	94.80	0.02	93.10	0.01	95.12	0.01			94.40	0.02	97.55	0.00	98.61	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1449382156
95.61	0.01	94.80	0.00	93.11	0.01	95.12	0.00			94.40	0.00	97.55	0.00	98.65	0.04	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1351098715
95.61	0.01	94.80	0.00	93.12	0.01	95.16	0.04			94.40	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.752511594
95.62	0.01	94.80	0.00	93.16	0.04	95.17	0.01			94.40	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3660832365
95.63	0.01	94.80	0.00	93.21	0.04	95.17	0.00			94.40	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2454090054
95.64	0.01	94.80	0.00	93.21	0.00	95.21	0.04			94.40	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2831707324
95.64	0.01	94.80	0.00	93.24	0.04	95.21	0.00			94.40	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1244676883
95.65	0.01	94.80	0.00	93.26	0.01	95.21	0.00			94.40	0.00	97.55	0.00	98.67	0.02	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1064633228
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95.77	0.01	94.84	0.00	93.54	0.00	95.46	0.00			94.41	0.00	97.55	0.00	98.81	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3191387176
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95.88	0.01	94.84	0.00	93.54	0.00	95.46	0.00			94.41	0.00	97.55	0.00	99.45	0.01	/workspace/coverage/default/65.chip_sw_all_escalation_resets.3782814176
95.88	0.01	94.84	0.00	93.54	0.00	95.46	0.00			94.41	0.00	97.55	0.00	99.46	0.01	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1541584298
95.88	0.01	94.84	0.00	93.54	0.00	95.46	0.00			94.41	0.00	97.55	0.00	99.47	0.01	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3227394658
95.88	0.01	94.84	0.00	93.54	0.00	95.46	0.00			94.41	0.00	97.55	0.00	99.48	0.01	/workspace/coverage/default/81.chip_sw_all_escalation_resets.1835973107
95.88	0.01	94.84	0.00	93.54	0.00	95.46	0.00			94.41	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/84.chip_sw_all_escalation_resets.3183667411
95.89	0.01	94.84	0.00	93.54	0.00	95.46	0.00			94.41	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.283620786
95.89	0.01	94.84	0.00	93.54	0.00	95.46	0.00			94.41	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3289020559
95.89	0.01	94.84	0.00	93.54	0.00	95.46	0.00			94.41	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/94.chip_sw_all_escalation_resets.494596607
95.89	0.01	94.84	0.00	93.54	0.00	95.46	0.00			94.41	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/95.chip_sw_all_escalation_resets.1496318146
95.89	0.01	94.84	0.00	93.55	0.01	95.47	0.01			94.41	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.1692186772
95.89	0.01	94.84	0.00	93.56	0.01	95.47	0.00			94.41	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.822980154
95.90	0.01	94.84	0.00	93.57	0.01	95.47	0.00			94.41	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.195407374
95.90	0.01	94.84	0.01	93.57	0.00	95.47	0.01			94.41	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/34.chip_sw_all_escalation_resets.3754343770
95.90	0.01	94.85	0.01	93.57	0.00	95.47	0.00			94.41	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.1806173997
95.90	0.01	94.85	0.00	93.57	0.00	95.48	0.01			94.41	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.4107748357
95.90	0.01	94.85	0.00	93.57	0.00	95.49	0.01			94.41	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2988192615
95.90	0.01	94.85	0.00	93.57	0.00	95.49	0.00			94.42	0.01	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2751802091
95.91	0.01	94.85	0.00	93.57	0.00	95.49	0.00			94.43	0.01	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.3054010846
95.91	0.01	94.85	0.00	93.58	0.01	95.49	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1693740690
95.91	0.01	94.85	0.00	93.59	0.01	95.49	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.848446537
95.91	0.01	94.85	0.00	93.59	0.01	95.49	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1872301211
95.91	0.01	94.85	0.00	93.60	0.01	95.49	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.2154324060
95.91	0.01	94.85	0.00	93.60	0.00	95.50	0.01			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4235081401
95.91	0.01	94.85	0.00	93.60	0.00	95.51	0.01			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.8408208
95.91	0.01	94.85	0.00	93.60	0.00	95.51	0.01			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_flash_init.4293808922
95.92	0.01	94.86	0.01	93.60	0.00	95.51	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2505750378
95.92	0.01	94.87	0.01	93.60	0.00	95.51	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.101379556
95.92	0.01	94.87	0.00	93.60	0.00	95.52	0.01			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1544423089
95.92	0.01	94.87	0.00	93.60	0.00	95.52	0.01			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.95311963
95.92	0.01	94.87	0.00	93.60	0.01	95.52	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_rw.3657761400
95.92	0.01	94.87	0.00	93.61	0.01	95.52	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.2371004694
95.92	0.01	94.87	0.00	93.61	0.01	95.52	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.956998522
95.92	0.01	94.87	0.00	93.61	0.01	95.52	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.3776646479
95.92	0.01	94.87	0.00	93.62	0.01	95.52	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.2402311239
95.92	0.01	94.87	0.00	93.62	0.01	95.52	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3690340626
95.92	0.01	94.87	0.00	93.63	0.01	95.52	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.4258886213
95.92	0.01	94.87	0.00	93.63	0.01	95.52	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3906274906
95.92	0.01	94.87	0.00	93.63	0.01	95.52	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2031491725
95.92	0.01	94.87	0.00	93.64	0.01	95.52	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2564415855
95.92	0.01	94.87	0.00	93.64	0.01	95.52	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/2.chip_sw_gpio.2786171915
95.92	0.01	94.87	0.00	93.64	0.00	95.52	0.01			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.1486566793
95.93	0.01	94.87	0.01	93.64	0.00	95.52	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.2320193182
95.93	0.01	94.87	0.01	93.64	0.00	95.52	0.00			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.196620208
95.93	0.01	94.87	0.00	93.64	0.00	95.53	0.01			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1809506379
95.93	0.01	94.87	0.00	93.64	0.00	95.53	0.01			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3191771472
95.93	0.01	94.87	0.00	93.64	0.00	95.53	0.01			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1408454291
95.93	0.01	94.87	0.00	93.64	0.00	95.53	0.01			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2820157061
95.93	0.01	94.87	0.00	93.64	0.00	95.54	0.01			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3774098627
95.93	0.01	94.87	0.00	93.64	0.00	95.54	0.01			94.43	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3190520422

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3669122121
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3774078448
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3814966914
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.768174261
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2517635532
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3920716006
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2644755338
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.4108235017
/workspace/coverage/cover_reg_top/0.xbar_error_random.3584833831
/workspace/coverage/cover_reg_top/0.xbar_random.30746046
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.4116729886
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3170792586
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3970768977
/workspace/coverage/cover_reg_top/0.xbar_same_source.515037951
/workspace/coverage/cover_reg_top/0.xbar_smoke.2013314603
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1141865681
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.823332400
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3475761954
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3942967089
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1252473071
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.4037813335
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2919232330
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2833609809
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3790672116
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.440763517
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3610084045
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3208466950
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2337128693
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2334529947
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2304821436
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2710238653
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2954529366
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1269466505
/workspace/coverage/cover_reg_top/1.xbar_error_random.1051831613
/workspace/coverage/cover_reg_top/1.xbar_random.1258996467
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.4141211428
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2489345456
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3113990409
/workspace/coverage/cover_reg_top/1.xbar_same_source.3684314758
/workspace/coverage/cover_reg_top/1.xbar_smoke.1088529539
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.523612885
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2838878841
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.905156742
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2273038600
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2211081157
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.259923763
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.400070637
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2582852432
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2422688999
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.675306057
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1895386165
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2530175853
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3356405376
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1275949295
/workspace/coverage/cover_reg_top/10.xbar_error_random.2549369632
/workspace/coverage/cover_reg_top/10.xbar_random.3862421609
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2691565500
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.949468601
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3227147151
/workspace/coverage/cover_reg_top/10.xbar_same_source.201738605
/workspace/coverage/cover_reg_top/10.xbar_smoke.1278750027
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.844648887
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.941714945
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1416832364
/workspace/coverage/cover_reg_top/10.xbar_stress_all.4257881827
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3023391416
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.244976793
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2004549395
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2075075382
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2942830556
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1369061629
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.476490705
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2640677813
/workspace/coverage/cover_reg_top/11.xbar_error_random.1582844803
/workspace/coverage/cover_reg_top/11.xbar_random.1587504156
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2801981656
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2974643672
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3434116335
/workspace/coverage/cover_reg_top/11.xbar_same_source.2619583640
/workspace/coverage/cover_reg_top/11.xbar_smoke.4235451667
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2428904002
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.33171208
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2276405419
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1458064778
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2316773718
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3585858261
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.575253283
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.879595949
/workspace/coverage/cover_reg_top/12.chip_csr_rw.3101132687
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2191162895
/workspace/coverage/cover_reg_top/12.chip_tl_errors.4212867099
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1365439631
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2316160492
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2071862784
/workspace/coverage/cover_reg_top/12.xbar_error_random.773193867
/workspace/coverage/cover_reg_top/12.xbar_random.3657110988
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3879809151
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.630076470
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.4215339807
/workspace/coverage/cover_reg_top/12.xbar_same_source.3157831100
/workspace/coverage/cover_reg_top/12.xbar_smoke.3547258230
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.722971333
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1509214728
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.35209423
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1616194233
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3346317382
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1372385587
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1501379467
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1241838828
/workspace/coverage/cover_reg_top/13.chip_csr_rw.370620982
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2572274061
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3201433729
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.418335258
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3494610008
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2049376073
/workspace/coverage/cover_reg_top/13.xbar_error_random.2914359518
/workspace/coverage/cover_reg_top/13.xbar_random.2511864229
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.592224607
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2716381983
/workspace/coverage/cover_reg_top/13.xbar_same_source.2363004073
/workspace/coverage/cover_reg_top/13.xbar_smoke.1190012148
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2526549540
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3800621536
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/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.615355078
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2002469945
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/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2367475885
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.592305825
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1800998136
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3993139655
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1009937685
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2983886571
/workspace/coverage/default/4.chip_sw_all_escalation_resets.15656359
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2893593821
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.116248212
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3803940557
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4126103786
/workspace/coverage/default/4.chip_sw_uart_tx_rx.410356677
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2185553366
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.762998250
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/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2095697141
/workspace/coverage/default/4.chip_tap_straps_dev.3879062726
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/workspace/coverage/default/4.chip_tap_straps_rma.1698889321
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3607468213
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1289979333
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.733030775
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/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2313894294
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/workspace/coverage/default/47.chip_sw_all_escalation_resets.2822601286
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.599142731
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1966848300
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1842820342
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2029842467
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.292995652
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2217677260
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1878919741
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3020002139
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3653162477
/workspace/coverage/default/50.chip_sw_all_escalation_resets.2585163368
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3272105487
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2175525015
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1254311397
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.69084053
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3353255509
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.77865605
/workspace/coverage/default/54.chip_sw_all_escalation_resets.3597289784
/workspace/coverage/default/55.chip_sw_all_escalation_resets.651761326
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1231279756
/workspace/coverage/default/56.chip_sw_all_escalation_resets.4147036300
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3011944364
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.952144246
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3354470555
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3434529830
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3850780885
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3032267838
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.825633191
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.399872963
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2108385485
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2215164005
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1491773679
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1586122244
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2494027445
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.4207739401
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3525892219
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.558802760
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1523123970
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3175484047
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.537454390
/workspace/coverage/default/67.chip_sw_all_escalation_resets.1352598519
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2042925568
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2240826439
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.655169314
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2356043233
/workspace/coverage/default/7.chip_sw_all_escalation_resets.1674798326
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3486454078
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.88602595
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.929173458
/workspace/coverage/default/70.chip_sw_all_escalation_resets.4213324127
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1964912858
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2833914499
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2439687291
/workspace/coverage/default/73.chip_sw_all_escalation_resets.835682341
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4068172409
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1729267347
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4223901974
/workspace/coverage/default/75.chip_sw_all_escalation_resets.95217253
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4106417312
/workspace/coverage/default/76.chip_sw_all_escalation_resets.106499022
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2954911249
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2571290571
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.930295791
/workspace/coverage/default/78.chip_sw_all_escalation_resets.309479367
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3171717442
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1468599899
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2223347709
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.4143343515
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3255201508
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2996534550
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3081919776
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2069308803
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1292668706
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2583003899
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2215835407
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3974385600
/workspace/coverage/default/83.chip_sw_all_escalation_resets.2389955944
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.956109430
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.780710888
/workspace/coverage/default/85.chip_sw_all_escalation_resets.563177420
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3270659567
/workspace/coverage/default/86.chip_sw_all_escalation_resets.872563925
/workspace/coverage/default/87.chip_sw_all_escalation_resets.4252985822
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.895600004
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2405986416
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2567068275
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2120256244
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1013714711
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3658983633
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3467736692
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2396071342
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2527755525
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2411754101
/workspace/coverage/default/93.chip_sw_all_escalation_resets.4080467629
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2137948047
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1232503551
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1789691997
/workspace/coverage/default/99.chip_sw_all_escalation_resets.493271350
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2461266009
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1366525154
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.140082897
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.300353921
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2180374241
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1676048048
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.917542695
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2485069699

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Total test records in report: 2884

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/2.chip_sw_rv_timer_irq.1729488399			Jun 29 07:57:15 PM PDT 24	Jun 29 08:02:13 PM PDT 24	3209574120 ps
T5	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3348427452			Jun 29 07:40:26 PM PDT 24	Jun 29 07:43:10 PM PDT 24	3466783248 ps
T6	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.752511594			Jun 29 07:39:15 PM PDT 24	Jun 29 07:49:46 PM PDT 24	6975947738 ps
T15	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3471100114			Jun 29 08:05:08 PM PDT 24	Jun 29 08:42:08 PM PDT 24	8684452660 ps
T82	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1929345180			Jun 29 07:44:32 PM PDT 24	Jun 29 07:55:09 PM PDT 24	4074348068 ps
T22	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.4100349205			Jun 29 07:53:53 PM PDT 24	Jun 29 08:06:26 PM PDT 24	6863917983 ps
T17	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.669940080			Jun 29 07:40:05 PM PDT 24	Jun 29 07:49:39 PM PDT 24	8097382616 ps
T16	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.877338670			Jun 29 07:44:17 PM PDT 24	Jun 29 11:20:40 PM PDT 24	254406154258 ps
T83	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4127812471			Jun 29 08:06:29 PM PDT 24	Jun 29 08:13:30 PM PDT 24	4010171792 ps
T84	/workspace/coverage/default/1.chip_sw_edn_auto_mode.1429518992			Jun 29 07:46:09 PM PDT 24	Jun 29 08:04:50 PM PDT 24	4593900280 ps
T111	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2320381896			Jun 29 07:54:21 PM PDT 24	Jun 29 08:07:54 PM PDT 24	4429794896 ps
T19	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2195897089			Jun 29 07:42:05 PM PDT 24	Jun 29 07:46:01 PM PDT 24	3020671447 ps
T192	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2162009061			Jun 29 07:40:30 PM PDT 24	Jun 29 07:49:42 PM PDT 24	3853609740 ps
T230	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3417717286			Jun 29 07:43:17 PM PDT 24	Jun 29 07:56:35 PM PDT 24	4841392336 ps
T56	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2085783097			Jun 29 07:59:14 PM PDT 24	Jun 29 08:08:59 PM PDT 24	3436708200 ps
T39	/workspace/coverage/default/72.chip_sw_all_escalation_resets.437897404			Jun 29 08:12:57 PM PDT 24	Jun 29 08:23:19 PM PDT 24	5328897786 ps
T78	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2665254496			Jun 29 07:58:02 PM PDT 24	Jun 29 08:02:58 PM PDT 24	3462064124 ps
T40	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1008232664			Jun 29 07:39:51 PM PDT 24	Jun 29 08:11:09 PM PDT 24	8752678984 ps
T63	/workspace/coverage/default/10.chip_sw_all_escalation_resets.842828985			Jun 29 08:07:58 PM PDT 24	Jun 29 08:24:03 PM PDT 24	5664831388 ps
T146	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3990655895			Jun 29 07:42:13 PM PDT 24	Jun 29 07:52:23 PM PDT 24	5091560488 ps
T109	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4041345422			Jun 29 07:53:42 PM PDT 24	Jun 29 08:11:57 PM PDT 24	6472224785 ps
T18	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1251082625			Jun 29 07:38:07 PM PDT 24	Jun 29 10:43:56 PM PDT 24	59043802156 ps
T285	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.4030510114			Jun 29 07:53:11 PM PDT 24	Jun 29 08:02:52 PM PDT 24	3743677480 ps
T164	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4036188606			Jun 29 07:43:43 PM PDT 24	Jun 29 08:45:36 PM PDT 24	17238079262 ps
T147	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1532322759			Jun 29 07:39:06 PM PDT 24	Jun 29 07:47:45 PM PDT 24	5044996408 ps
T286	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3894944830			Jun 29 07:58:25 PM PDT 24	Jun 29 08:03:47 PM PDT 24	2846115816 ps
T52	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3746653523			Jun 29 07:45:49 PM PDT 24	Jun 29 08:56:06 PM PDT 24	15948153160 ps
T55	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3356053358			Jun 29 07:43:37 PM PDT 24	Jun 29 07:53:13 PM PDT 24	5760775984 ps
T277	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3531169166			Jun 29 07:41:24 PM PDT 24	Jun 29 07:52:18 PM PDT 24	4147431080 ps
T62	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4115525501			Jun 29 07:55:49 PM PDT 24	Jun 29 08:37:41 PM PDT 24	29487875650 ps
T196	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1800998136			Jun 29 08:08:45 PM PDT 24	Jun 29 08:18:59 PM PDT 24	5413642350 ps
T53	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1133574032			Jun 29 07:46:38 PM PDT 24	Jun 29 08:45:23 PM PDT 24	11559749986 ps
T157	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1604356795			Jun 29 07:56:53 PM PDT 24	Jun 29 08:07:58 PM PDT 24	4981183310 ps
T656	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3645728211			Jun 29 07:39:33 PM PDT 24	Jun 29 07:44:53 PM PDT 24	2967406074 ps
T669	/workspace/coverage/default/2.chip_sw_hmac_smoketest.3935633396			Jun 29 08:02:21 PM PDT 24	Jun 29 08:07:26 PM PDT 24	3249819090 ps
T54	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2341969566			Jun 29 08:07:49 PM PDT 24	Jun 29 09:16:05 PM PDT 24	15973611808 ps
T667	/workspace/coverage/default/0.chip_sw_aes_smoketest.2796376977			Jun 29 07:39:20 PM PDT 24	Jun 29 07:44:31 PM PDT 24	2735849368 ps
T185	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3641557042			Jun 29 07:40:30 PM PDT 24	Jun 29 07:58:22 PM PDT 24	8193536097 ps
T67	/workspace/coverage/default/3.chip_tap_straps_rma.453341668			Jun 29 08:02:31 PM PDT 24	Jun 29 08:12:10 PM PDT 24	6115529311 ps
T274	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.4262861556			Jun 29 07:40:36 PM PDT 24	Jun 29 07:58:24 PM PDT 24	7195773988 ps
T275	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1506387846			Jun 29 07:40:57 PM PDT 24	Jun 29 07:47:23 PM PDT 24	3073737848 ps
T276	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.4075455375			Jun 29 07:55:58 PM PDT 24	Jun 29 08:03:35 PM PDT 24	4184201148 ps
T219	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3763947448			Jun 29 07:39:08 PM PDT 24	Jun 29 07:52:31 PM PDT 24	7176311844 ps
T1	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.974301237			Jun 29 07:49:52 PM PDT 24	Jun 29 08:20:23 PM PDT 24	22336690576 ps
T97	/workspace/coverage/default/0.chip_sw_kmac_idle.2339373412			Jun 29 07:40:08 PM PDT 24	Jun 29 07:45:42 PM PDT 24	2716001630 ps
T98	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2106498715			Jun 29 08:07:15 PM PDT 24	Jun 29 08:33:52 PM PDT 24	9374869458 ps
T99	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1858994222			Jun 29 08:00:07 PM PDT 24	Jun 29 08:15:12 PM PDT 24	4644899400 ps
T100	/workspace/coverage/default/14.chip_sw_all_escalation_resets.1626658774			Jun 29 08:07:13 PM PDT 24	Jun 29 08:16:16 PM PDT 24	4998977962 ps
T101	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2060084946			Jun 29 08:07:27 PM PDT 24	Jun 29 09:02:08 PM PDT 24	13141507384 ps
T68	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.446877111			Jun 29 07:59:22 PM PDT 24	Jun 29 11:12:12 PM PDT 24	60137384440 ps
T102	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.528535176			Jun 29 07:47:52 PM PDT 24	Jun 29 07:59:29 PM PDT 24	7331385120 ps
T103	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1727979616			Jun 29 07:58:39 PM PDT 24	Jun 29 08:31:55 PM PDT 24	9583166600 ps
T104	/workspace/coverage/default/1.chip_plic_all_irqs_20.2848502594			Jun 29 07:48:07 PM PDT 24	Jun 29 08:00:44 PM PDT 24	4487999564 ps
T516	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2439687291			Jun 29 08:12:51 PM PDT 24	Jun 29 08:19:29 PM PDT 24	3131693736 ps
T517	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2209362609			Jun 29 08:13:03 PM PDT 24	Jun 29 08:19:25 PM PDT 24	3255922336 ps
T278	/workspace/coverage/default/27.chip_sw_all_escalation_resets.3365790283			Jun 29 08:08:09 PM PDT 24	Jun 29 08:19:07 PM PDT 24	5045506266 ps
T347	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1964912858			Jun 29 08:13:09 PM PDT 24	Jun 29 08:20:42 PM PDT 24	3520820144 ps
T357	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2048084144			Jun 29 07:39:03 PM PDT 24	Jun 29 07:54:23 PM PDT 24	7960129020 ps
T358	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2070279898			Jun 29 07:44:59 PM PDT 24	Jun 29 07:48:39 PM PDT 24	2479986384 ps
T25	/workspace/coverage/default/0.chip_sw_gpio.1755264002			Jun 29 07:39:16 PM PDT 24	Jun 29 07:46:05 PM PDT 24	3893751348 ps
T113	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2093143678			Jun 29 07:39:08 PM PDT 24	Jun 29 07:41:06 PM PDT 24	2207087604 ps
T359	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2058848386			Jun 29 07:54:04 PM PDT 24	Jun 29 08:13:43 PM PDT 24	6055917777 ps
T194	/workspace/coverage/default/4.chip_tap_straps_prod.3902956147			Jun 29 08:04:33 PM PDT 24	Jun 29 08:07:35 PM PDT 24	2617041192 ps
T360	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1947173302			Jun 29 07:44:01 PM PDT 24	Jun 29 07:54:06 PM PDT 24	4614498086 ps
T28	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2961516244			Jun 29 07:40:35 PM PDT 24	Jun 29 09:45:25 PM PDT 24	32168292904 ps
T195	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2963213334			Jun 29 07:57:30 PM PDT 24	Jun 29 08:26:50 PM PDT 24	16139041602 ps
T137	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3443146940			Jun 29 08:04:18 PM PDT 24	Jun 29 08:14:30 PM PDT 24	4371528080 ps
T829	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2479009199			Jun 29 07:44:06 PM PDT 24	Jun 29 07:48:18 PM PDT 24	3086117731 ps
T444	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1289052317			Jun 29 07:43:32 PM PDT 24	Jun 29 08:00:41 PM PDT 24	5843781676 ps
T105	/workspace/coverage/default/2.chip_sw_power_sleep_load.2577475709			Jun 29 08:02:38 PM PDT 24	Jun 29 08:10:57 PM PDT 24	5335878078 ps
T26	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1653924315			Jun 29 07:53:27 PM PDT 24	Jun 29 08:25:16 PM PDT 24	7986703383 ps
T830	/workspace/coverage/default/2.chip_sw_edn_sw_mode.2105986627			Jun 29 07:57:00 PM PDT 24	Jun 29 08:23:42 PM PDT 24	5890672112 ps
T301	/workspace/coverage/default/1.chip_sw_uart_tx_rx.2117083574			Jun 29 07:42:10 PM PDT 24	Jun 29 07:53:36 PM PDT 24	4656001500 ps
T199	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1212774774			Jun 29 07:44:10 PM PDT 24	Jun 29 08:07:59 PM PDT 24	6955947810 ps
T79	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2269127382			Jun 29 07:59:45 PM PDT 24	Jun 29 08:22:37 PM PDT 24	10632481178 ps
T2	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2419949325			Jun 29 07:51:39 PM PDT 24	Jun 29 08:15:19 PM PDT 24	23267933898 ps
T518	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.870051321			Jun 29 07:52:52 PM PDT 24	Jun 29 07:58:17 PM PDT 24	3087869936 ps
T138	/workspace/coverage/default/0.chip_sw_power_idle_load.2836927375			Jun 29 07:41:23 PM PDT 24	Jun 29 07:53:32 PM PDT 24	4117371816 ps
T80	/workspace/coverage/default/69.chip_sw_all_escalation_resets.2484131590			Jun 29 08:12:14 PM PDT 24	Jun 29 08:21:51 PM PDT 24	5174063540 ps
T86	/workspace/coverage/default/1.chip_sw_plic_sw_irq.2796692154			Jun 29 07:48:24 PM PDT 24	Jun 29 07:54:59 PM PDT 24	2930246808 ps
T87	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1223804314			Jun 29 07:44:04 PM PDT 24	Jun 29 07:48:22 PM PDT 24	2834990964 ps
T76	/workspace/coverage/default/0.chip_jtag_mem_access.3167171290			Jun 29 07:30:25 PM PDT 24	Jun 29 07:52:29 PM PDT 24	13261901828 ps
T88	/workspace/coverage/default/66.chip_sw_all_escalation_resets.3175484047			Jun 29 08:12:39 PM PDT 24	Jun 29 08:22:09 PM PDT 24	5555147030 ps
T89	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2540170871			Jun 29 07:49:24 PM PDT 24	Jun 29 07:59:16 PM PDT 24	3779253678 ps
T90	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1643255766			Jun 29 07:47:03 PM PDT 24	Jun 29 08:11:06 PM PDT 24	10492540215 ps
T58	/workspace/coverage/default/1.chip_sw_alert_test.407874422			Jun 29 07:46:30 PM PDT 24	Jun 29 07:51:29 PM PDT 24	3421770420 ps
T91	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1666071985			Jun 29 07:38:40 PM PDT 24	Jun 29 07:58:42 PM PDT 24	5125112168 ps
T92	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2893593821			Jun 29 08:05:42 PM PDT 24	Jun 29 08:13:54 PM PDT 24	7037995376 ps
T27	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2124529356			Jun 29 07:37:08 PM PDT 24	Jun 29 07:46:20 PM PDT 24	4006855638 ps
T441	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3655647393			Jun 29 08:02:47 PM PDT 24	Jun 29 08:06:20 PM PDT 24	2951939714 ps
T72	/workspace/coverage/default/0.chip_jtag_csr_rw.2336238962			Jun 29 07:30:30 PM PDT 24	Jun 29 07:52:25 PM PDT 24	12470680438 ps
T70	/workspace/coverage/default/0.chip_sw_usbdev_pullup.888313903			Jun 29 07:38:32 PM PDT 24	Jun 29 07:43:31 PM PDT 24	2814652350 ps
T110	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.989731371			Jun 29 07:50:53 PM PDT 24	Jun 29 09:02:00 PM PDT 24	24651874511 ps
T61	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1163850457			Jun 29 07:41:42 PM PDT 24	Jun 29 07:49:55 PM PDT 24	5397653500 ps
T114	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3026776410			Jun 29 07:39:29 PM PDT 24	Jun 29 07:42:07 PM PDT 24	2994801755 ps
T173	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2522357017			Jun 29 07:56:22 PM PDT 24	Jun 29 07:58:19 PM PDT 24	1865984594 ps
T831	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.200265824			Jun 29 07:42:54 PM PDT 24	Jun 29 07:58:30 PM PDT 24	5543503060 ps
T323	/workspace/coverage/default/97.chip_sw_all_escalation_resets.1232503551			Jun 29 08:13:56 PM PDT 24	Jun 29 08:23:16 PM PDT 24	5781280768 ps
T703	/workspace/coverage/default/62.chip_sw_all_escalation_resets.2494027445			Jun 29 08:11:26 PM PDT 24	Jun 29 08:24:05 PM PDT 24	6311787672 ps
T158	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3242371955			Jun 29 07:43:02 PM PDT 24	Jun 29 07:53:40 PM PDT 24	4512280005 ps
T336	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3096420614			Jun 29 07:54:18 PM PDT 24	Jun 29 08:05:04 PM PDT 24	5673958240 ps
T697	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4075590089			Jun 29 08:08:15 PM PDT 24	Jun 29 08:14:44 PM PDT 24	4215379796 ps
T702	/workspace/coverage/default/99.chip_sw_all_escalation_resets.493271350			Jun 29 08:14:27 PM PDT 24	Jun 29 08:23:30 PM PDT 24	4336451642 ps
T832	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3487962336			Jun 29 07:57:41 PM PDT 24	Jun 29 08:09:48 PM PDT 24	6583976521 ps
T29	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2764072366			Jun 29 07:56:55 PM PDT 24	Jun 29 08:23:37 PM PDT 24	22415217128 ps
T49	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3202171993			Jun 29 07:45:25 PM PDT 24	Jun 29 08:51:17 PM PDT 24	14951677771 ps
T324	/workspace/coverage/default/25.chip_sw_all_escalation_resets.415491646			Jun 29 08:08:29 PM PDT 24	Jun 29 08:24:38 PM PDT 24	6266194920 ps
T833	/workspace/coverage/default/2.chip_sw_aes_smoketest.4244707111			Jun 29 08:08:54 PM PDT 24	Jun 29 08:13:27 PM PDT 24	3172959780 ps
T133	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1499065909			Jun 29 07:56:26 PM PDT 24	Jun 29 08:09:24 PM PDT 24	9294356252 ps
T316	/workspace/coverage/default/2.chip_sival_flash_info_access.3674950995			Jun 29 07:52:46 PM PDT 24	Jun 29 07:58:02 PM PDT 24	3166834610 ps
T834	/workspace/coverage/default/0.chip_sw_csrng_smoketest.1883379261			Jun 29 07:39:56 PM PDT 24	Jun 29 07:43:05 PM PDT 24	2820312912 ps
T197	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1575204411			Jun 29 07:45:59 PM PDT 24	Jun 29 08:05:19 PM PDT 24	5803661416 ps
T320	/workspace/coverage/default/1.chip_sival_flash_info_access.998905474			Jun 29 07:43:04 PM PDT 24	Jun 29 07:48:41 PM PDT 24	2901526800 ps
T132	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1697098458			Jun 29 08:01:27 PM PDT 24	Jun 29 08:07:51 PM PDT 24	5007543540 ps
T366	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.175737282			Jun 29 07:42:11 PM PDT 24	Jun 29 08:12:00 PM PDT 24	7316563684 ps
T64	/workspace/coverage/default/4.chip_tap_straps_testunlock0.3607468213			Jun 29 08:04:34 PM PDT 24	Jun 29 08:09:57 PM PDT 24	3560249834 ps
T835	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2937459282			Jun 29 07:41:48 PM PDT 24	Jun 29 07:48:20 PM PDT 24	6135752554 ps
T836	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2000610870			Jun 29 07:58:09 PM PDT 24	Jun 29 08:01:44 PM PDT 24	3196718346 ps
T318	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2571762929			Jun 29 07:58:15 PM PDT 24	Jun 29 08:04:50 PM PDT 24	2680491977 ps
T706	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2954911249			Jun 29 08:22:25 PM PDT 24	Jun 29 08:28:57 PM PDT 24	3907235912 ps
T189	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.149647883			Jun 29 07:57:22 PM PDT 24	Jun 29 08:07:40 PM PDT 24	5203809228 ps
T106	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1765278350			Jun 29 07:56:53 PM PDT 24	Jun 29 08:07:14 PM PDT 24	19946486182 ps
T186	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1596152227			Jun 29 07:41:37 PM PDT 24	Jun 29 07:47:00 PM PDT 24	2819127950 ps
T154	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1259411548			Jun 29 07:41:58 PM PDT 24	Jun 29 10:56:55 PM PDT 24	59813143655 ps
T267	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4103054433			Jun 29 07:44:12 PM PDT 24	Jun 29 07:55:14 PM PDT 24	4120465844 ps
T268	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.828056491			Jun 29 07:43:54 PM PDT 24	Jun 29 08:51:23 PM PDT 24	15742112184 ps
T269	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.3073995747			Jun 29 07:54:42 PM PDT 24	Jun 29 08:13:36 PM PDT 24	5766527848 ps
T270	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2065489279			Jun 29 07:52:30 PM PDT 24	Jun 29 07:57:21 PM PDT 24	2978967756 ps
T191	/workspace/coverage/default/1.chip_sw_pattgen_ios.196620208			Jun 29 07:41:43 PM PDT 24	Jun 29 07:45:59 PM PDT 24	2554834520 ps
T187	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2315469456			Jun 29 08:01:02 PM PDT 24	Jun 29 08:06:02 PM PDT 24	3502799752 ps
T271	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2778341857			Jun 29 07:42:12 PM PDT 24	Jun 29 08:11:38 PM PDT 24	8562636590 ps
T234	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3191771472			Jun 29 07:38:03 PM PDT 24	Jun 29 09:35:18 PM PDT 24	26954303240 ps
T69	/workspace/coverage/default/2.chip_tap_straps_testunlock0.732032091			Jun 29 07:59:09 PM PDT 24	Jun 29 08:06:51 PM PDT 24	4818180682 ps
T165	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2001316202			Jun 29 07:37:55 PM PDT 24	Jun 29 08:54:10 PM PDT 24	18083055798 ps
T118	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.4235077179			Jun 29 08:02:49 PM PDT 24	Jun 29 08:12:16 PM PDT 24	6068935184 ps
T693	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2082775675			Jun 29 08:06:59 PM PDT 24	Jun 29 08:12:51 PM PDT 24	3578577720 ps
T311	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.726939500			Jun 29 07:40:48 PM PDT 24	Jun 29 08:12:13 PM PDT 24	10838312930 ps
T340	/workspace/coverage/default/2.chip_sw_aon_timer_irq.12325566			Jun 29 07:56:52 PM PDT 24	Jun 29 08:04:50 PM PDT 24	4640015750 ps
T350	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.772096080			Jun 29 07:50:39 PM PDT 24	Jun 29 07:59:55 PM PDT 24	5808620730 ps
T198	/workspace/coverage/default/12.chip_sw_all_escalation_resets.3093823646			Jun 29 08:06:19 PM PDT 24	Jun 29 08:17:27 PM PDT 24	6154050730 ps
T686	/workspace/coverage/default/28.chip_sw_all_escalation_resets.673994146			Jun 29 08:08:57 PM PDT 24	Jun 29 08:20:07 PM PDT 24	6171546664 ps
T382	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1079743136			Jun 29 08:03:58 PM PDT 24	Jun 29 08:11:27 PM PDT 24	6328837898 ps
T3	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3725387851			Jun 29 08:02:51 PM PDT 24	Jun 29 08:35:37 PM PDT 24	23679196644 ps
T50	/workspace/coverage/default/1.rom_e2e_shutdown_output.482899183			Jun 29 08:01:18 PM PDT 24	Jun 29 09:10:47 PM PDT 24	28107666797 ps
T837	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3233493828			Jun 29 07:49:51 PM PDT 24	Jun 29 07:59:30 PM PDT 24	4748649856 ps
T770	/workspace/coverage/default/40.chip_sw_all_escalation_resets.3345491929			Jun 29 08:09:28 PM PDT 24	Jun 29 08:20:59 PM PDT 24	4325338368 ps
T175	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1142602461			Jun 29 07:41:03 PM PDT 24	Jun 29 08:00:59 PM PDT 24	6975346312 ps
T838	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.324278749			Jun 29 08:01:57 PM PDT 24	Jun 29 08:05:21 PM PDT 24	2973946536 ps
T696	/workspace/coverage/default/21.chip_sw_all_escalation_resets.3154553946			Jun 29 08:07:58 PM PDT 24	Jun 29 08:19:05 PM PDT 24	5282970028 ps
T698	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2313894294			Jun 29 08:09:11 PM PDT 24	Jun 29 08:15:33 PM PDT 24	3240419448 ps
T159	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.881546247			Jun 29 07:40:22 PM PDT 24	Jun 29 07:46:27 PM PDT 24	3896725117 ps
T344	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1878919741			Jun 29 08:04:36 PM PDT 24	Jun 29 08:21:23 PM PDT 24	12889028337 ps
T7	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2565293332			Jun 29 07:39:14 PM PDT 24	Jun 29 07:48:50 PM PDT 24	3908000360 ps
T432	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.645342999			Jun 29 07:41:18 PM PDT 24	Jun 29 07:45:21 PM PDT 24	3344943244 ps
T433	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3853696795			Jun 29 07:44:47 PM PDT 24	Jun 29 07:55:58 PM PDT 24	6446793488 ps
T434	/workspace/coverage/default/45.chip_sw_all_escalation_resets.3351459778			Jun 29 08:11:14 PM PDT 24	Jun 29 08:21:19 PM PDT 24	5728978838 ps
T435	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.686046740			Jun 29 07:54:40 PM PDT 24	Jun 29 08:00:17 PM PDT 24	3374413420 ps
T319	/workspace/coverage/default/1.chip_sw_hmac_enc.772833928			Jun 29 07:45:31 PM PDT 24	Jun 29 07:49:38 PM PDT 24	3232761994 ps
T436	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3630049902			Jun 29 07:59:07 PM PDT 24	Jun 29 08:08:29 PM PDT 24	4860411757 ps
T326	/workspace/coverage/default/64.chip_sw_all_escalation_resets.704410321			Jun 29 08:12:27 PM PDT 24	Jun 29 08:23:48 PM PDT 24	5061788850 ps
T218	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2011761892			Jun 29 08:04:12 PM PDT 24	Jun 29 08:20:18 PM PDT 24	6319272060 ps
T243	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1455847654			Jun 29 08:06:41 PM PDT 24	Jun 29 08:24:20 PM PDT 24	11664686458 ps
T32	/workspace/coverage/default/0.chip_sw_usbdev_config_host.1680332517			Jun 29 07:39:56 PM PDT 24	Jun 29 08:16:23 PM PDT 24	7851949400 ps
T183	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2167913854			Jun 29 07:47:06 PM PDT 24	Jun 29 07:55:51 PM PDT 24	3661970840 ps
T244	/workspace/coverage/default/79.chip_sw_all_escalation_resets.1468599899			Jun 29 08:22:54 PM PDT 24	Jun 29 08:31:26 PM PDT 24	5867447864 ps
T245	/workspace/coverage/default/2.rom_e2e_smoke.161156348			Jun 29 08:06:42 PM PDT 24	Jun 29 09:09:26 PM PDT 24	15299879888 ps
T246	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2481472981			Jun 29 07:59:25 PM PDT 24	Jun 29 08:24:38 PM PDT 24	6331462786 ps
T247	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.467452464			Jun 29 07:53:37 PM PDT 24	Jun 29 08:01:45 PM PDT 24	5592825208 ps
T119	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.371059492			Jun 29 08:00:06 PM PDT 24	Jun 29 08:21:12 PM PDT 24	8896437874 ps
T248	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1292668706			Jun 29 08:13:17 PM PDT 24	Jun 29 08:21:26 PM PDT 24	4464229904 ps
T679	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1131639603			Jun 29 08:10:36 PM PDT 24	Jun 29 08:18:44 PM PDT 24	4132445800 ps
T839	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.487698754			Jun 29 07:55:48 PM PDT 24	Jun 29 08:58:57 PM PDT 24	15114171732 ps
T200	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.840207986			Jun 29 07:54:48 PM PDT 24	Jun 29 08:11:50 PM PDT 24	6300458718 ps
T699	/workspace/coverage/default/90.chip_sw_all_escalation_resets.2527755525			Jun 29 08:14:31 PM PDT 24	Jun 29 08:25:23 PM PDT 24	4504022432 ps
T155	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.3766325255			Jun 29 07:40:37 PM PDT 24	Jun 29 11:02:24 PM PDT 24	62955430961 ps
T450	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.67358576			Jun 29 07:40:21 PM PDT 24	Jun 29 07:48:55 PM PDT 24	5174921336 ps
T840	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3267603697			Jun 29 07:39:44 PM PDT 24	Jun 29 07:48:11 PM PDT 24	5737037750 ps
T841	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3803554818			Jun 29 07:43:23 PM PDT 24	Jun 29 07:50:44 PM PDT 24	3980480312 ps
T112	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3269340551			Jun 29 07:44:40 PM PDT 24	Jun 29 07:52:28 PM PDT 24	4715486598 ps
T842	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1299213819			Jun 29 07:39:06 PM PDT 24	Jun 29 07:46:39 PM PDT 24	5592696672 ps
T229	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.81025067			Jun 29 08:02:57 PM PDT 24	Jun 29 08:07:16 PM PDT 24	2782647480 ps
T77	/workspace/coverage/default/1.chip_jtag_csr_rw.187471254			Jun 29 07:42:06 PM PDT 24	Jun 29 07:47:18 PM PDT 24	4361379440 ps
T843	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1603894369			Jun 29 07:56:53 PM PDT 24	Jun 29 09:07:14 PM PDT 24	15573618116 ps
T844	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.748492095			Jun 29 08:06:49 PM PDT 24	Jun 29 09:17:20 PM PDT 24	14604802536 ps
T184	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1336705579			Jun 29 07:52:51 PM PDT 24	Jun 29 08:03:31 PM PDT 24	5724768109 ps
T704	/workspace/coverage/default/2.chip_sw_flash_crash_alert.582700865			Jun 29 08:01:45 PM PDT 24	Jun 29 08:14:10 PM PDT 24	6301343778 ps
T203	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1963184418			Jun 29 07:40:00 PM PDT 24	Jun 29 08:19:02 PM PDT 24	12006898691 ps
T34	/workspace/coverage/default/1.chip_sw_gpio.1313241739			Jun 29 07:43:48 PM PDT 24	Jun 29 07:53:49 PM PDT 24	4015762036 ps
T766	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1656579222			Jun 29 08:11:37 PM PDT 24	Jun 29 08:18:43 PM PDT 24	4437255558 ps
T845	/workspace/coverage/default/2.chip_sw_kmac_idle.1421183399			Jun 29 07:57:42 PM PDT 24	Jun 29 08:01:27 PM PDT 24	3022681500 ps
T249	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2176283669			Jun 29 07:59:09 PM PDT 24	Jun 29 08:10:52 PM PDT 24	4898138688 ps
T846	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.563374020			Jun 29 07:48:05 PM PDT 24	Jun 29 07:55:42 PM PDT 24	4773458308 ps
T292	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3063966093			Jun 29 07:42:57 PM PDT 24	Jun 29 07:58:42 PM PDT 24	5082754900 ps
T847	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.666461323			Jun 29 07:39:16 PM PDT 24	Jun 29 07:43:08 PM PDT 24	2815772586 ps
T57	/workspace/coverage/default/2.chip_jtag_csr_rw.615944440			Jun 29 07:52:41 PM PDT 24	Jun 29 08:10:50 PM PDT 24	9097965140 ps
T848	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.828600188			Jun 29 07:45:36 PM PDT 24	Jun 29 09:06:28 PM PDT 24	15215536400 ps
T176	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2840991928			Jun 29 07:42:28 PM PDT 24	Jun 29 09:16:10 PM PDT 24	46927488300 ps
T231	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2568939590			Jun 29 07:41:25 PM PDT 24	Jun 29 08:30:47 PM PDT 24	31422767605 ps
T849	/workspace/coverage/default/1.rom_keymgr_functest.2087480796			Jun 29 07:51:46 PM PDT 24	Jun 29 08:03:47 PM PDT 24	4451372170 ps
T30	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.244746830			Jun 29 07:39:36 PM PDT 24	Jun 29 08:14:57 PM PDT 24	23235743364 ps
T850	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1676148631			Jun 29 08:00:05 PM PDT 24	Jun 29 08:16:13 PM PDT 24	10900608064 ps
T700	/workspace/coverage/default/6.chip_sw_all_escalation_resets.3850780885			Jun 29 08:04:38 PM PDT 24	Jun 29 08:17:56 PM PDT 24	4505008620 ps
T287	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.716808311			Jun 29 07:58:33 PM PDT 24	Jun 29 08:09:25 PM PDT 24	5191975982 ps
T668	/workspace/coverage/default/1.chip_sw_power_sleep_load.238450496			Jun 29 07:51:03 PM PDT 24	Jun 29 08:02:11 PM PDT 24	11149600444 ps
T348	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.176648945			Jun 29 08:10:13 PM PDT 24	Jun 29 08:18:07 PM PDT 24	3296770070 ps
T339	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2662638764			Jun 29 07:44:43 PM PDT 24	Jun 29 07:54:51 PM PDT 24	18127158920 ps
T337	/workspace/coverage/default/34.chip_sw_all_escalation_resets.3754343770			Jun 29 08:08:32 PM PDT 24	Jun 29 08:21:55 PM PDT 24	5614382156 ps
T851	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2955536910			Jun 29 08:03:37 PM PDT 24	Jun 29 08:07:13 PM PDT 24	2078911940 ps
T852	/workspace/coverage/default/2.chip_sw_power_idle_load.1186505461			Jun 29 08:00:44 PM PDT 24	Jun 29 08:13:04 PM PDT 24	3767496000 ps
T120	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3803940557			Jun 29 08:05:04 PM PDT 24	Jun 29 08:14:57 PM PDT 24	4659180808 ps
T250	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.117155038			Jun 29 07:38:53 PM PDT 24	Jun 29 07:50:59 PM PDT 24	7441198174 ps
T853	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.591239100			Jun 29 08:06:59 PM PDT 24	Jun 29 08:14:06 PM PDT 24	3932368280 ps
T349	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1523123970			Jun 29 08:13:44 PM PDT 24	Jun 29 08:21:45 PM PDT 24	3714980660 ps
T854	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.439436600			Jun 29 07:56:47 PM PDT 24	Jun 29 08:22:13 PM PDT 24	10731853659 ps
T170	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2831707324			Jun 29 07:55:39 PM PDT 24	Jun 29 07:58:47 PM PDT 24	2719116369 ps
T333	/workspace/coverage/default/71.chip_sw_all_escalation_resets.2833914499			Jun 29 08:12:14 PM PDT 24	Jun 29 08:21:47 PM PDT 24	5319810280 ps
T107	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1873033056			Jun 29 07:51:50 PM PDT 24	Jun 29 08:32:25 PM PDT 24	14937589740 ps
T181	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.669087296			Jun 29 07:50:58 PM PDT 24	Jun 29 08:08:03 PM PDT 24	8884233749 ps
T93	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2465529821			Jun 29 08:00:47 PM PDT 24	Jun 29 08:27:44 PM PDT 24	26579653710 ps
T201	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2786029589			Jun 29 07:59:13 PM PDT 24	Jun 29 08:37:47 PM PDT 24	13016902910 ps
T855	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4039517756			Jun 29 07:39:06 PM PDT 24	Jun 29 08:00:17 PM PDT 24	6569385896 ps
T447	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.709018643			Jun 29 08:01:51 PM PDT 24	Jun 29 09:13:27 PM PDT 24	24580483181 ps
T642	/workspace/coverage/default/0.chip_tap_straps_dev.3054010846			Jun 29 07:38:54 PM PDT 24	Jun 29 07:50:20 PM PDT 24	6687557271 ps
T371	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1534633800			Jun 29 07:45:17 PM PDT 24	Jun 29 09:26:56 PM PDT 24	23354255400 ps
T856	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.148378843			Jun 29 07:40:58 PM PDT 24	Jun 29 07:47:13 PM PDT 24	4791699274 ps
T857	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.4125312174			Jun 29 08:05:00 PM PDT 24	Jun 29 09:01:06 PM PDT 24	11087498110 ps
T115	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3575432331			Jun 29 07:38:40 PM PDT 24	Jun 29 07:50:19 PM PDT 24	4124422416 ps
T858	/workspace/coverage/default/0.chip_sw_csrng_kat_test.4043496580			Jun 29 07:39:49 PM PDT 24	Jun 29 07:42:57 PM PDT 24	2698865624 ps
T859	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.661109234			Jun 29 07:38:34 PM PDT 24	Jun 29 07:52:23 PM PDT 24	8327046504 ps
T860	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2066674895			Jun 29 07:40:04 PM PDT 24	Jun 29 07:56:59 PM PDT 24	5856947056 ps
T861	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2653289700			Jun 29 07:39:21 PM PDT 24	Jun 29 08:50:55 PM PDT 24	17225754750 ps
T862	/workspace/coverage/default/2.chip_sw_otbn_randomness.1048411742			Jun 29 07:57:28 PM PDT 24	Jun 29 08:15:15 PM PDT 24	6255255460 ps
T23	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3205735895			Jun 29 07:54:35 PM PDT 24	Jun 29 08:04:08 PM PDT 24	3973289847 ps
T327	/workspace/coverage/default/17.chip_sw_all_escalation_resets.244498320			Jun 29 08:08:15 PM PDT 24	Jun 29 08:21:36 PM PDT 24	5651171196 ps
T341	/workspace/coverage/default/1.chip_sw_aon_timer_irq.4135183666			Jun 29 07:43:54 PM PDT 24	Jun 29 07:49:57 PM PDT 24	4309055492 ps
T863	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3542361993			Jun 29 07:45:09 PM PDT 24	Jun 29 08:13:35 PM PDT 24	7231524804 ps
T864	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2877640959			Jun 29 07:48:29 PM PDT 24	Jun 29 09:11:13 PM PDT 24	18955144018 ps
T289	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1872301211			Jun 29 07:42:34 PM PDT 24	Jun 29 07:53:43 PM PDT 24	5175278519 ps
T334	/workspace/coverage/default/56.chip_sw_all_escalation_resets.4147036300			Jun 29 08:10:34 PM PDT 24	Jun 29 08:21:37 PM PDT 24	4630183832 ps
T222	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2031491725			Jun 29 07:39:35 PM PDT 24	Jun 29 08:08:22 PM PDT 24	11295311356 ps
T865	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.687793053			Jun 29 07:56:03 PM PDT 24	Jun 29 08:16:41 PM PDT 24	7063409287 ps
T866	/workspace/coverage/default/1.chip_sw_hmac_oneshot.1458141464			Jun 29 07:48:46 PM PDT 24	Jun 29 07:55:13 PM PDT 24	3782931880 ps
T867	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1236736679			Jun 29 07:57:07 PM PDT 24	Jun 29 09:02:45 PM PDT 24	17650515012 ps
T868	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1356348024			Jun 29 07:49:48 PM PDT 24	Jun 29 08:00:58 PM PDT 24	3293003480 ps
T869	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2416610323			Jun 29 07:39:56 PM PDT 24	Jun 29 07:43:56 PM PDT 24	3299958744 ps
T228	/workspace/coverage/default/0.chip_sw_plic_sw_irq.1806173997			Jun 29 07:39:59 PM PDT 24	Jun 29 07:46:31 PM PDT 24	3723801708 ps
T177	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1544423089			Jun 29 07:38:31 PM PDT 24	Jun 29 07:47:14 PM PDT 24	4824303624 ps
T24	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.4278008805			Jun 29 07:41:04 PM PDT 24	Jun 29 07:45:02 PM PDT 24	2634697842 ps
T701	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1541584298			Jun 29 08:22:11 PM PDT 24	Jun 29 08:29:43 PM PDT 24	4011638910 ps
T695	/workspace/coverage/default/44.chip_sw_all_escalation_resets.829102066			Jun 29 08:11:06 PM PDT 24	Jun 29 08:21:23 PM PDT 24	5212671762 ps