Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	144202	1			T73	85		T74	4		T75	5
values[2]	12046	1			T117	1		T490	1		T226	1
values[3]	5215	1			T524	21		T632	5		T400	23
values[4]	3125	1			T524	14		T632	8		T400	3
values[5]	2077	1			T524	10		T632	14		T783	21
values[6]	1360	1			T524	5		T632	5		T783	29
values[7]	852	1			T524	5		T632	5		T783	4
values[8]	583	1			T524	4		T632	17		T637	8
values[9]	460	1			T524	8		T632	4		T637	10
values[10]	362	1			T524	5		T632	10		T637	12
values[11]	326	1			T524	9		T632	3		T637	14
values[12]	250	1			T524	5		T632	12		T637	2
values[13]	226	1			T524	9		T632	5		T674	1
values[14]	292	1			T524	9		T632	10		T674	5
values[15]	282	1			T524	4		T632	8		T674	6
values[16]	233	1			T524	9		T632	4		T674	2
values[17]	264	1			T524	27		T632	3		T674	9
values[18]	219	1			T524	16		T632	9		T674	11
values[19]	210	1			T524	3		T632	17		T674	3
values[20]	227	1			T524	4		T632	7		T674	1
values[21]	212	1			T524	2		T632	3		T674	2
values[22]	238	1			T632	4		T674	1		T476	2
values[23]	216	1			T632	5		T674	2		T476	4
values[24]	192	1			T632	6		T674	2		T476	10
values[25]	219	1			T632	6		T674	2		T476	1
values[26]	171	1			T632	6		T674	4		T476	1
values[27]	196	1			T632	13		T674	2		T476	1
values[28]	213	1			T632	11		T674	1		T476	2
values[29]	224	1			T632	8		T674	3		T476	1
values[30]	195	1			T632	7		T674	7		T476	3
values[31]	186	1			T632	3		T674	3		T476	1
values[32]	210	1			T632	4		T674	6		T476	4
values[33]	212	1			T632	6		T674	6		T476	7
values[34]	216	1			T632	3		T674	3		T476	5
values[35]	180	1			T632	4		T476	3		T775	1
values[36]	196	1			T632	13		T476	7		T775	1
values[37]	219	1			T632	6		T476	4		T775	1
values[38]	198	1			T632	5		T476	5		T775	1
values[39]	177	1			T632	20		T476	5		T775	1
values[40]	180	1			T632	6		T476	4		T775	1
values[41]	187	1			T632	3		T476	4		T775	1
values[42]	160	1			T632	3		T476	4		T775	1
values[43]	181	1			T632	16		T476	5		T775	1
values[44]	183	1			T632	5		T476	6		T775	1
values[45]	175	1			T632	5		T476	3		T775	1
values[46]	169	1			T632	6		T476	8		T775	1
values[47]	166	1			T632	7		T476	7		T775	1
values[48]	200	1			T632	17		T476	2		T775	1
values[49]	194	1			T632	5		T476	1		T775	1
values[50]	169	1			T632	3		T476	2		T775	1
values[51]	177	1			T632	3		T476	4		T775	1
values[52]	164	1			T632	7		T476	2		T775	1
values[53]	159	1			T632	7		T476	2		T775	1
values[54]	150	1			T632	5		T476	1		T775	1
values[55]	156	1			T632	11		T476	1		T775	1
values[56]	156	1			T632	5		T476	2		T775	1
values[57]	175	1			T632	8		T476	1		T775	1
values[58]	183	1			T632	15		T476	3		T775	1
values[59]	183	1			T632	8		T476	3		T775	1
values[60]	155	1			T632	25		T476	1		T775	1
values[61]	158	1			T632	14		T476	2		T775	1
values[62]	145	1			T632	1		T476	4		T775	1
values[63]	135	1			T476	3		T775	1		T482	1
values[64]	112	1			T476	2		T775	1		T482	1
values[65]	83	1			T476	4		T775	1		T482	1
values[66]	101	1			T476	4		T775	1		T482	1
values[67]	90	1			T476	2		T775	1		T482	1
values[68]	82	1			T476	7		T775	1		T482	1
values[69]	93	1			T476	2		T775	1		T482	1
values[70]	74	1			T476	2		T775	1		T482	1
values[71]	52	1			T476	2		T775	1		T482	1
values[72]	76	1			T476	1		T775	1		T482	1
values[73]	72	1			T476	5		T775	1		T482	1
values[74]	72	1			T476	7		T775	1		T482	1
values[75]	70	1			T476	8		T775	1		T482	1
values[76]	62	1			T476	10		T775	1		T482	1
values[77]	55	1			T476	6		T775	1		T482	1
values[78]	62	1			T476	3		T775	1		T482	1
values[79]	96	1			T476	2		T775	1		T482	1
values[80]	77	1			T775	1		T482	1		T628	20
values[81]	69	1			T775	1		T482	1		T628	12
values[82]	81	1			T775	1		T482	8		T628	3
values[83]	66	1			T775	1		T482	2		T628	11
values[84]	59	1			T775	1		T482	4		T628	10
values[85]	58	1			T775	1		T482	2		T628	2
values[86]	88	1			T775	1		T482	6		T628	7
values[87]	67	1			T775	1		T482	2		T628	4
values[88]	60	1			T775	2		T482	1		T628	4
values[89]	49	1			T775	1		T482	2		T628	5
values[90]	57	1			T775	1		T482	3		T628	7
values[91]	57	1			T775	3		T482	2		T628	7
values[92]	69	1			T775	5		T482	1		T628	10
values[93]	74	1			T775	3		T482	5		T628	5
values[94]	57	1			T775	2		T482	1		T628	4
values[95]	59	1			T775	2		T482	5		T628	2
values[96]	59	1			T775	4		T482	2		T628	5
values[97]	73	1			T775	1		T482	3		T628	6
values[98]	69	1			T775	2		T482	1		T628	4
values[99]	72	1			T775	1		T482	2		T628	5
values[100]	45	1			T775	1		T482	1		T628	3
values[101]	54	1			T775	3		T482	1		T628	5
values[102]	56	1			T775	1		T482	1		T628	11
values[103]	65	1			T775	3		T482	3		T628	3
values[104]	55	1			T775	2		T482	1		T628	11
values[105]	55	1			T775	2		T482	6		T628	6
values[106]	58	1			T775	2		T482	6		T628	7
values[107]	52	1			T775	3		T482	1		T628	6
values[108]	43	1			T775	1		T482	2		T628	8
values[109]	55	1			T775	2		T482	5		T628	6
values[110]	52	1			T775	3		T482	4		T628	9
values[111]	57	1			T775	3		T482	2		T628	10
values[112]	39	1			T775	1		T482	2		T628	4
values[113]	45	1			T775	1		T482	4		T628	4
values[114]	61	1			T775	1		T482	1		T628	6
values[115]	53	1			T775	1		T482	1		T628	3
values[116]	46	1			T775	3		T482	3		T628	6
values[117]	45	1			T775	2		T482	2		T628	10
values[118]	42	1			T775	4		T482	2		T628	7
values[119]	57	1			T775	2		T482	1		T628	19
values[120]	46	1			T775	2		T482	3		T628	13
values[121]	36	1			T775	1		T482	1		T628	6
values[122]	31	1			T775	2		T482	1		T628	2
values[123]	45	1			T775	1		T482	6		T628	5
values[124]	37	1			T775	1		T482	4		T628	2
values[125]	55	1			T775	2		T482	1		T628	9
values[126]	81	1			T775	5		T482	2		T628	40
values[127]	584	1			T775	48		T482	22		T628	71
values[128]	4756	1			T775	335		T482	292		T628	20