Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145290	1			T73	98		T74	5		T75	5
values[2]	11158	1			T73	1		T368	2		T225	5
values[3]	4332	1			T523	1		T527	1		T528	1
values[4]	2430	1			T527	1		T528	1		T524	26
values[5]	1592	1			T527	1		T528	1		T524	23
values[6]	1188	1			T527	1		T528	1		T524	13
values[7]	940	1			T527	1		T528	1		T524	16
values[8]	726	1			T527	1		T528	1		T524	13
values[9]	517	1			T527	1		T528	1		T524	13
values[10]	383	1			T527	1		T528	1		T524	4
values[11]	314	1			T527	1		T528	1		T524	3
values[12]	317	1			T527	1		T528	1		T524	3
values[13]	327	1			T527	1		T528	1		T524	4
values[14]	339	1			T527	1		T528	1		T524	5
values[15]	329	1			T527	1		T528	1		T524	3
values[16]	288	1			T527	1		T528	1		T524	3
values[17]	333	1			T527	1		T528	1		T524	3
values[18]	286	1			T527	1		T528	1		T524	7
values[19]	257	1			T527	1		T528	1		T524	5
values[20]	358	1			T527	1		T528	1		T524	2
values[21]	283	1			T527	1		T528	1		T524	1
values[22]	282	1			T527	1		T528	1		T524	1
values[23]	278	1			T527	1		T528	1		T524	3
values[24]	328	1			T527	1		T528	1		T524	1
values[25]	313	1			T527	1		T528	1		T632	9
values[26]	254	1			T527	1		T528	1		T632	5
values[27]	270	1			T527	1		T528	1		T632	8
values[28]	257	1			T527	1		T528	1		T632	3
values[29]	280	1			T527	1		T528	1		T632	12
values[30]	266	1			T527	1		T528	1		T632	8
values[31]	291	1			T527	1		T528	1		T632	5
values[32]	319	1			T527	1		T528	1		T632	4
values[33]	280	1			T527	1		T528	1		T632	8
values[34]	271	1			T527	1		T528	1		T632	22
values[35]	275	1			T527	1		T528	1		T632	7
values[36]	263	1			T527	1		T528	1		T632	5
values[37]	282	1			T527	1		T528	1		T632	9
values[38]	269	1			T527	1		T528	1		T632	9
values[39]	280	1			T527	1		T528	1		T632	4
values[40]	230	1			T527	1		T528	1		T632	4
values[41]	286	1			T527	1		T528	1		T632	11
values[42]	318	1			T527	1		T528	1		T632	5
values[43]	254	1			T527	1		T528	1		T632	5
values[44]	257	1			T527	1		T528	1		T632	3
values[45]	295	1			T527	1		T528	1		T632	7
values[46]	326	1			T527	1		T528	1		T632	6
values[47]	306	1			T527	1		T528	1		T632	4
values[48]	279	1			T527	1		T528	1		T632	8
values[49]	253	1			T527	1		T528	1		T632	5
values[50]	214	1			T527	1		T528	1		T632	6
values[51]	267	1			T527	1		T528	1		T632	7
values[52]	240	1			T527	1		T528	1		T632	23
values[53]	218	1			T527	1		T528	1		T632	9
values[54]	192	1			T527	1		T528	1		T632	8
values[55]	170	1			T527	1		T528	1		T632	8
values[56]	180	1			T527	1		T528	1		T632	5
values[57]	177	1			T527	1		T528	1		T632	5
values[58]	210	1			T527	1		T528	1		T632	4
values[59]	159	1			T527	1		T528	1		T632	4
values[60]	143	1			T527	1		T528	1		T632	4
values[61]	186	1			T527	1		T528	1		T632	6
values[62]	143	1			T527	1		T528	1		T632	6
values[63]	151	1			T527	1		T528	1		T632	6
values[64]	150	1			T527	1		T528	1		T632	7
values[65]	130	1			T527	1		T528	1		T632	2
values[66]	117	1			T527	1		T528	1		T632	4
values[67]	119	1			T527	2		T528	1		T455	5
values[68]	87	1			T527	1		T528	1		T455	7
values[69]	109	1			T527	1		T528	2		T455	5
values[70]	105	1			T527	1		T528	1		T455	7
values[71]	101	1			T527	1		T528	1		T455	8
values[72]	92	1			T527	1		T528	1		T455	6
values[73]	80	1			T527	1		T528	1		T455	7
values[74]	70	1			T527	1		T528	1		T777	1
values[75]	76	1			T527	1		T528	1		T777	1
values[76]	59	1			T527	1		T528	1		T777	1
values[77]	49	1			T527	1		T528	1		T777	1
values[78]	55	1			T527	1		T528	1		T777	1
values[79]	43	1			T527	1		T528	1		T777	1
values[80]	63	1			T527	1		T528	1		T777	1
values[81]	53	1			T527	1		T528	1		T777	1
values[82]	53	1			T527	1		T528	1		T777	1
values[83]	76	1			T527	1		T528	1		T777	1
values[84]	64	1			T527	1		T528	1		T777	1
values[85]	57	1			T527	1		T528	1		T777	2
values[86]	57	1			T527	1		T528	1		T777	1
values[87]	65	1			T527	1		T528	1		T777	5
values[88]	66	1			T527	1		T528	1		T777	4
values[89]	65	1			T527	1		T528	1		T777	5
values[90]	72	1			T527	1		T528	1		T777	1
values[91]	64	1			T527	1		T528	1		T777	1
values[92]	72	1			T527	1		T528	1		T777	4
values[93]	70	1			T527	1		T528	1		T777	2
values[94]	61	1			T527	1		T528	1		T777	2
values[95]	51	1			T527	1		T528	3		T777	2
values[96]	55	1			T527	1		T528	7		T777	1
values[97]	54	1			T527	1		T528	1		T777	1
values[98]	69	1			T527	1		T528	2		T777	1
values[99]	73	1			T527	1		T528	15		T777	2
values[100]	59	1			T527	1		T528	4		T777	2
values[101]	54	1			T527	1		T528	3		T777	1
values[102]	54	1			T527	1		T528	5		T777	2
values[103]	60	1			T527	1		T528	1		T777	1
values[104]	60	1			T527	1		T528	1		T777	2
values[105]	53	1			T527	1		T528	2		T777	1
values[106]	57	1			T527	1		T528	3		T777	3
values[107]	54	1			T527	1		T528	2		T777	3
values[108]	47	1			T527	1		T528	3		T777	7
values[109]	43	1			T527	1		T528	1		T777	3
values[110]	55	1			T527	1		T528	1		T777	1
values[111]	47	1			T527	1		T528	3		T777	2
values[112]	57	1			T527	1		T528	2		T777	4
values[113]	51	1			T527	1		T528	1		T777	9
values[114]	41	1			T527	1		T528	1		T777	1
values[115]	52	1			T527	1		T528	1		T777	4
values[116]	51	1			T527	1		T528	3		T777	4
values[117]	54	1			T527	1		T528	2		T777	11
values[118]	34	1			T527	1		T528	1		T777	1
values[119]	34	1			T527	1		T528	1		T777	2
values[120]	43	1			T527	1		T528	3		T777	1
values[121]	39	1			T527	1		T528	1		T777	1
values[122]	39	1			T527	1		T528	2		T777	2
values[123]	54	1			T527	1		T528	1		T777	3
values[124]	51	1			T527	1		T528	2		T777	3
values[125]	53	1			T527	2		T528	5		T777	4
values[126]	121	1			T527	1		T528	1		T777	2
values[127]	679	1			T527	26		T528	28		T777	26
values[128]	5931	1			T527	293		T528	334		T777	309