Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139194	1			T73	94		T74	4		T75	4
values[2]	7335	1			T117	1		T226	9		T420	2
values[3]	3543	1			T226	1		T528	1		T400	38
values[4]	2101	1			T528	1		T400	12		T785	17
values[5]	1359	1			T528	1		T400	16		T785	7
values[6]	958	1			T528	1		T400	20		T455	28
values[7]	731	1			T528	1		T400	26		T455	16
values[8]	611	1			T528	1		T400	22		T455	22
values[9]	498	1			T528	1		T400	6		T455	32
values[10]	489	1			T528	1		T400	5		T455	27
values[11]	557	1			T528	1		T400	11		T455	14
values[12]	502	1			T528	1		T455	26		T637	6
values[13]	480	1			T528	1		T455	16		T637	21
values[14]	388	1			T528	1		T455	7		T637	7
values[15]	401	1			T528	1		T455	8		T637	18
values[16]	409	1			T528	1		T455	11		T637	7
values[17]	436	1			T528	1		T455	7		T637	4
values[18]	427	1			T528	1		T455	21		T637	6
values[19]	457	1			T528	1		T455	13		T637	7
values[20]	422	1			T528	1		T455	9		T637	5
values[21]	476	1			T528	1		T455	22		T637	7
values[22]	461	1			T528	1		T455	14		T637	10
values[23]	383	1			T528	1		T455	14		T637	7
values[24]	332	1			T528	1		T455	6		T637	7
values[25]	292	1			T528	1		T455	14		T637	11
values[26]	289	1			T528	1		T455	4		T637	5
values[27]	348	1			T528	1		T455	22		T637	14
values[28]	405	1			T528	1		T455	4		T637	17
values[29]	377	1			T528	1		T455	13		T637	10
values[30]	318	1			T528	1		T455	8		T637	9
values[31]	321	1			T528	1		T455	17		T637	8
values[32]	294	1			T528	1		T455	17		T637	7
values[33]	309	1			T528	1		T455	4		T637	11
values[34]	338	1			T528	1		T455	5		T637	12
values[35]	362	1			T528	1		T455	10		T637	14
values[36]	290	1			T528	1		T455	7		T637	8
values[37]	312	1			T528	1		T455	8		T637	8
values[38]	313	1			T528	1		T455	6		T637	14
values[39]	315	1			T528	2		T455	18		T637	22
values[40]	377	1			T528	1		T455	15		T637	10
values[41]	309	1			T528	1		T455	6		T637	4
values[42]	261	1			T528	1		T455	9		T637	5
values[43]	312	1			T528	1		T455	8		T637	5
values[44]	257	1			T528	1		T455	4		T637	5
values[45]	270	1			T528	1		T455	8		T637	7
values[46]	279	1			T528	1		T455	12		T637	8
values[47]	306	1			T528	1		T455	10		T637	9
values[48]	230	1			T528	1		T455	10		T637	7
values[49]	143	1			T528	1		T455	10		T637	10
values[50]	182	1			T528	1		T455	15		T637	10
values[51]	136	1			T528	1		T455	6		T637	13
values[52]	116	1			T528	1		T637	18		T775	1
values[53]	130	1			T528	1		T637	13		T775	1
values[54]	114	1			T528	1		T637	5		T775	1
values[55]	122	1			T528	1		T637	11		T775	1
values[56]	74	1			T528	1		T637	4		T775	1
values[57]	48	1			T528	1		T637	3		T775	1
values[58]	60	1			T528	1		T775	1		T585	3
values[59]	61	1			T528	1		T775	1		T585	3
values[60]	53	1			T528	1		T775	1		T585	6
values[61]	56	1			T528	1		T775	1		T585	11
values[62]	48	1			T528	1		T775	1		T585	2
values[63]	56	1			T528	1		T775	1		T585	1
values[64]	70	1			T528	1		T775	1		T585	3
values[65]	73	1			T528	1		T775	1		T585	10
values[66]	85	1			T528	1		T775	1		T585	6
values[67]	62	1			T528	1		T775	1		T585	1
values[68]	76	1			T528	1		T775	1		T585	3
values[69]	60	1			T528	1		T775	1		T585	2
values[70]	59	1			T528	1		T775	1		T585	2
values[71]	53	1			T528	1		T775	1		T585	10
values[72]	50	1			T528	1		T775	1		T585	7
values[73]	53	1			T528	1		T775	1		T585	1
values[74]	52	1			T528	1		T775	1		T585	7
values[75]	58	1			T528	1		T775	1		T585	8
values[76]	44	1			T528	1		T775	1		T585	7
values[77]	59	1			T528	1		T775	1		T585	6
values[78]	54	1			T528	1		T775	1		T585	3
values[79]	50	1			T528	1		T775	1		T585	1
values[80]	61	1			T528	1		T775	1		T585	6
values[81]	60	1			T528	1		T775	1		T585	8
values[82]	54	1			T528	1		T775	1		T585	4
values[83]	62	1			T528	1		T775	1		T585	3
values[84]	63	1			T528	1		T775	1		T585	3
values[85]	78	1			T528	1		T775	1		T585	6
values[86]	75	1			T528	1		T775	1		T585	6
values[87]	76	1			T528	1		T775	1		T585	7
values[88]	69	1			T528	1		T775	1		T585	4
values[89]	77	1			T528	1		T775	1		T585	6
values[90]	71	1			T528	1		T775	1		T585	5
values[91]	58	1			T528	1		T775	1		T585	10
values[92]	61	1			T528	1		T775	1		T585	8
values[93]	68	1			T528	1		T775	1		T585	11
values[94]	81	1			T528	1		T775	1		T585	10
values[95]	53	1			T528	1		T775	1		T585	3
values[96]	48	1			T528	1		T775	1		T585	1
values[97]	55	1			T528	1		T775	1		T802	4
values[98]	49	1			T528	1		T775	1		T802	2
values[99]	39	1			T528	1		T775	1		T802	4
values[100]	41	1			T528	1		T775	1		T802	9
values[101]	35	1			T528	2		T775	1		T802	4
values[102]	39	1			T528	2		T775	1		T802	4
values[103]	42	1			T528	2		T775	1		T802	2
values[104]	44	1			T528	3		T775	1		T802	3
values[105]	45	1			T528	4		T775	1		T802	3
values[106]	49	1			T528	4		T775	1		T802	11
values[107]	40	1			T528	4		T775	1		T802	4
values[108]	42	1			T528	4		T775	1		T802	3
values[109]	53	1			T528	9		T775	1		T802	3
values[110]	54	1			T528	2		T775	5		T802	6
values[111]	58	1			T528	1		T775	1		T802	2
values[112]	54	1			T528	1		T775	3		T802	5
values[113]	53	1			T528	2		T775	2		T802	3
values[114]	46	1			T528	3		T775	3		T802	4
values[115]	64	1			T528	2		T775	8		T802	6
values[116]	47	1			T528	2		T775	2		T802	3
values[117]	54	1			T528	1		T775	2		T802	8
values[118]	49	1			T528	1		T775	1		T802	6
values[119]	50	1			T528	4		T775	1		T802	7
values[120]	48	1			T528	1		T775	1		T802	2
values[121]	51	1			T528	1		T775	2		T802	2
values[122]	63	1			T528	2		T775	6		T802	5
values[123]	51	1			T528	1		T775	1		T802	3
values[124]	59	1			T528	4		T775	1		T802	5
values[125]	70	1			T528	1		T775	1		T802	9
values[126]	130	1			T528	2		T775	3		T802	6
values[127]	1333	1			T528	71		T775	69		T802	113
values[128]	6054	1			T528	345		T775	337		T802	543