Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	155457	1			T73	89		T74	1		T75	6
values[2]	5612	1			T117	1		T226	4		T420	2
values[3]	2723	1			T519	16		T781	1		T524	51
values[4]	1931	1			T519	10		T781	1		T524	61
values[5]	1408	1			T519	23		T781	1		T524	51
values[6]	1217	1			T519	26		T781	1		T524	59
values[7]	943	1			T519	27		T781	1		T524	62
values[8]	826	1			T519	34		T781	1		T524	53
values[9]	759	1			T519	49		T781	1		T524	37
values[10]	601	1			T519	60		T781	1		T524	27
values[11]	615	1			T519	46		T781	1		T524	21
values[12]	602	1			T519	31		T781	1		T524	26
values[13]	464	1			T519	16		T781	1		T524	42
values[14]	441	1			T519	22		T781	1		T524	66
values[15]	389	1			T519	18		T781	1		T524	41
values[16]	326	1			T519	11		T781	1		T524	39
values[17]	254	1			T781	1		T524	7		T410	1
values[18]	218	1			T781	1		T524	9		T410	1
values[19]	241	1			T781	1		T524	13		T410	1
values[20]	257	1			T781	1		T524	24		T410	2
values[21]	241	1			T781	1		T524	23		T410	1
values[22]	234	1			T781	1		T524	34		T410	4
values[23]	262	1			T781	1		T524	43		T410	4
values[24]	266	1			T781	1		T524	15		T410	3
values[25]	265	1			T781	1		T524	7		T410	4
values[26]	262	1			T781	1		T524	4		T410	2
values[27]	250	1			T781	1		T524	6		T410	2
values[28]	238	1			T781	1		T524	11		T410	1
values[29]	217	1			T781	1		T524	5		T410	3
values[30]	183	1			T781	1		T524	2		T410	3
values[31]	224	1			T781	1		T524	2		T410	1
values[32]	231	1			T781	1		T524	5		T410	4
values[33]	204	1			T781	1		T524	3		T410	3
values[34]	206	1			T781	1		T524	4		T410	10
values[35]	213	1			T781	1		T524	2		T410	4
values[36]	226	1			T781	1		T524	2		T410	3
values[37]	166	1			T781	1		T524	3		T410	6
values[38]	186	1			T781	1		T524	3		T410	2
values[39]	170	1			T781	1		T524	1		T410	2
values[40]	134	1			T781	1		T524	2		T410	3
values[41]	124	1			T781	1		T524	5		T410	1
values[42]	133	1			T781	1		T524	9		T410	1
values[43]	106	1			T781	1		T524	6		T410	1
values[44]	107	1			T781	1		T524	2		T410	3
values[45]	101	1			T781	1		T524	2		T410	2
values[46]	72	1			T781	1		T524	2		T410	2
values[47]	74	1			T781	1		T524	2		T410	2
values[48]	73	1			T781	1		T524	3		T410	1
values[49]	69	1			T781	1		T524	1		T410	2
values[50]	63	1			T781	1		T524	2		T410	4
values[51]	56	1			T781	1		T524	1		T410	1
values[52]	51	1			T781	1		T524	1		T410	5
values[53]	58	1			T781	1		T524	1		T410	2
values[54]	70	1			T781	1		T524	1		T410	1
values[55]	66	1			T781	1		T524	4		T410	2
values[56]	62	1			T781	1		T524	7		T410	2
values[57]	46	1			T781	1		T524	1		T410	1
values[58]	51	1			T781	1		T524	1		T410	3
values[59]	50	1			T781	1		T524	1		T410	1
values[60]	52	1			T781	1		T524	2		T410	2
values[61]	53	1			T781	2		T524	6		T410	4
values[62]	62	1			T781	1		T524	5		T410	2
values[63]	49	1			T781	1		T524	4		T410	1
values[64]	49	1			T781	1		T524	1		T410	1
values[65]	56	1			T781	1		T524	3		T410	3
values[66]	74	1			T781	1		T524	2		T410	3
values[67]	70	1			T781	1		T524	2		T410	2
values[68]	54	1			T781	1		T524	3		T410	3
values[69]	64	1			T781	1		T524	2		T410	3
values[70]	55	1			T781	1		T524	2		T410	1
values[71]	63	1			T781	1		T524	6		T410	2
values[72]	64	1			T781	1		T524	1		T410	2
values[73]	67	1			T781	1		T524	3		T410	2
values[74]	41	1			T781	1		T524	2		T410	2
values[75]	44	1			T781	1		T524	1		T410	2
values[76]	53	1			T781	1		T524	4		T410	2
values[77]	58	1			T781	1		T524	2		T410	1
values[78]	54	1			T781	1		T524	3		T410	3
values[79]	51	1			T781	1		T524	2		T410	3
values[80]	50	1			T781	1		T524	2		T410	2
values[81]	58	1			T781	1		T524	1		T410	1
values[82]	54	1			T781	1		T524	4		T410	4
values[83]	83	1			T781	1		T524	4		T410	1
values[84]	67	1			T781	1		T524	6		T410	1
values[85]	67	1			T781	1		T524	4		T410	2
values[86]	52	1			T781	1		T524	2		T410	3
values[87]	57	1			T781	1		T524	2		T410	3
values[88]	65	1			T781	1		T524	4		T410	6
values[89]	63	1			T781	1		T524	9		T410	3
values[90]	75	1			T781	1		T524	7		T410	4
values[91]	76	1			T781	1		T524	2		T410	7
values[92]	75	1			T781	1		T524	2		T410	6
values[93]	54	1			T781	1		T524	2		T410	4
values[94]	61	1			T781	1		T524	1		T410	3
values[95]	65	1			T781	1		T524	3		T410	1
values[96]	70	1			T781	1		T524	2		T410	2
values[97]	61	1			T781	1		T524	2		T410	3
values[98]	63	1			T781	1		T524	2		T410	6
values[99]	69	1			T781	1		T524	2		T410	2
values[100]	77	1			T781	1		T524	7		T410	7
values[101]	74	1			T781	1		T524	5		T410	3
values[102]	71	1			T781	1		T524	2		T410	1
values[103]	82	1			T781	1		T524	2		T410	2
values[104]	86	1			T781	1		T524	1		T410	8
values[105]	78	1			T781	1		T524	3		T410	2
values[106]	87	1			T781	1		T524	4		T410	2
values[107]	73	1			T781	1		T524	2		T410	1
values[108]	84	1			T781	1		T524	4		T410	3
values[109]	69	1			T781	1		T524	2		T410	4
values[110]	93	1			T781	1		T524	4		T410	1
values[111]	94	1			T781	1		T524	2		T410	2
values[112]	100	1			T781	1		T524	1		T410	5
values[113]	81	1			T781	1		T524	1		T410	3
values[114]	82	1			T781	1		T524	1		T410	2
values[115]	98	1			T781	1		T524	5		T410	7
values[116]	96	1			T781	1		T524	5		T410	5
values[117]	95	1			T781	1		T524	3		T410	3
values[118]	92	1			T781	1		T524	4		T410	6
values[119]	87	1			T781	1		T524	2		T410	6
values[120]	88	1			T781	1		T524	1		T410	1
values[121]	102	1			T781	1		T524	1		T410	2
values[122]	83	1			T781	1		T524	2		T410	6
values[123]	112	1			T781	2		T524	10		T410	9
values[124]	261	1			T781	3		T524	31		T410	13
values[125]	451	1			T781	2		T524	52		T410	31
values[126]	774	1			T781	12		T524	81		T410	51
values[127]	2066	1			T781	90		T524	43		T410	32
values[128]	3313	1			T781	192		T524	3		T410	2