Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	164182	1			T73	91		T74	4		T75	4
values[2]	4306	1			T73	1		T226	5		T488	3
values[3]	2123	1			T524	6		T506	1		T463	2
values[4]	1594	1			T524	8		T439	3		T537	55
values[5]	1187	1			T524	8		T439	1		T537	40
values[6]	1040	1			T524	11		T439	1		T537	18
values[7]	885	1			T524	5		T439	4		T537	8
values[8]	705	1			T524	4		T439	8		T537	1
values[9]	665	1			T524	7		T439	1		T498	27
values[10]	585	1			T524	7		T439	1		T498	20
values[11]	609	1			T524	4		T439	2		T498	48
values[12]	544	1			T524	3		T439	2		T498	52
values[13]	441	1			T524	3		T439	1		T498	35
values[14]	423	1			T524	3		T439	2		T498	22
values[15]	397	1			T524	2		T439	2		T498	23
values[16]	406	1			T524	4		T439	1		T498	18
values[17]	342	1			T524	1		T439	1		T498	9
values[18]	302	1			T524	1		T439	1		T498	4
values[19]	232	1			T524	1		T439	2		T498	4
values[20]	206	1			T524	1		T439	1		T498	4
values[21]	174	1			T524	3		T439	4		T498	2
values[22]	151	1			T524	4		T439	1		T498	1
values[23]	127	1			T524	1		T439	1		T498	2
values[24]	154	1			T524	2		T439	6		T498	2
values[25]	159	1			T524	3		T439	1		T498	1
values[26]	145	1			T524	2		T439	3		T498	1
values[27]	149	1			T524	2		T439	2		T498	1
values[28]	136	1			T524	4		T439	2		T498	2
values[29]	146	1			T524	6		T439	2		T498	3
values[30]	105	1			T524	3		T439	2		T498	3
values[31]	88	1			T524	2		T439	3		T498	1
values[32]	114	1			T524	1		T439	4		T498	2
values[33]	84	1			T524	2		T439	2		T498	1
values[34]	65	1			T524	3		T439	1		T498	1
values[35]	68	1			T524	3		T439	4		T498	4
values[36]	87	1			T524	7		T439	5		T498	3
values[37]	72	1			T524	9		T439	1		T498	2
values[38]	54	1			T524	3		T439	2		T498	1
values[39]	70	1			T524	1		T439	1		T498	1
values[40]	64	1			T524	2		T439	3		T498	1
values[41]	54	1			T524	4		T439	3		T498	2
values[42]	62	1			T524	2		T439	1		T498	2
values[43]	74	1			T524	7		T439	3		T498	2
values[44]	80	1			T524	5		T439	3		T498	3
values[45]	74	1			T524	1		T439	3		T498	2
values[46]	81	1			T524	3		T439	2		T498	7
values[47]	78	1			T524	1		T439	1		T498	5
values[48]	72	1			T524	2		T439	5		T498	1
values[49]	70	1			T524	1		T439	3		T498	1
values[50]	58	1			T524	7		T439	4		T498	1
values[51]	56	1			T524	9		T439	2		T498	2
values[52]	52	1			T524	5		T439	1		T498	2
values[53]	49	1			T524	1		T439	1		T498	1
values[54]	46	1			T524	4		T439	2		T498	3
values[55]	51	1			T524	1		T439	5		T498	2
values[56]	50	1			T524	2		T439	2		T498	2
values[57]	53	1			T524	1		T439	1		T498	3
values[58]	54	1			T524	1		T439	1		T498	10
values[59]	50	1			T524	3		T439	1		T498	2
values[60]	50	1			T524	1		T439	2		T498	1
values[61]	51	1			T524	2		T439	2		T498	2
values[62]	49	1			T524	3		T439	1		T498	2
values[63]	57	1			T524	1		T439	2		T498	1
values[64]	55	1			T524	2		T439	2		T498	2
values[65]	45	1			T524	2		T439	6		T498	2
values[66]	51	1			T524	4		T439	3		T498	1
values[67]	56	1			T524	1		T439	4		T498	4
values[68]	45	1			T524	1		T439	3		T498	5
values[69]	56	1			T524	4		T439	4		T498	7
values[70]	50	1			T524	2		T439	3		T498	3
values[71]	46	1			T524	1		T439	1		T498	4
values[72]	46	1			T524	1		T439	2		T498	3
values[73]	48	1			T524	3		T439	3		T498	2
values[74]	43	1			T524	1		T439	1		T498	4
values[75]	37	1			T524	3		T439	1		T498	2
values[76]	44	1			T524	1		T439	2		T498	2
values[77]	61	1			T524	4		T439	1		T498	4
values[78]	61	1			T524	2		T439	2		T498	2
values[79]	64	1			T524	3		T439	3		T498	1
values[80]	66	1			T524	2		T439	6		T498	1
values[81]	75	1			T524	2		T439	4		T498	2
values[82]	75	1			T524	1		T439	2		T498	1
values[83]	65	1			T524	1		T439	1		T498	3
values[84]	63	1			T524	3		T439	1		T498	2
values[85]	71	1			T524	3		T439	3		T498	2
values[86]	76	1			T524	1		T439	6		T498	3
values[87]	82	1			T524	3		T439	6		T498	4
values[88]	62	1			T524	3		T439	6		T498	6
values[89]	56	1			T524	2		T439	3		T498	2
values[90]	51	1			T524	1		T439	2		T498	1
values[91]	83	1			T524	2		T439	6		T498	2
values[92]	72	1			T524	1		T439	9		T498	1
values[93]	65	1			T524	3		T439	4		T498	4
values[94]	85	1			T524	6		T439	3		T498	4
values[95]	91	1			T524	5		T439	1		T498	2
values[96]	80	1			T524	7		T439	4		T498	2
values[97]	80	1			T524	1		T439	9		T498	5
values[98]	71	1			T524	2		T439	7		T498	5
values[99]	66	1			T524	2		T439	2		T498	3
values[100]	91	1			T524	2		T439	8		T498	4
values[101]	83	1			T524	6		T439	4		T498	13
values[102]	78	1			T524	2		T439	4		T498	9
values[103]	90	1			T524	1		T439	3		T498	12
values[104]	91	1			T524	2		T439	3		T498	11
values[105]	73	1			T524	3		T439	4		T498	8
values[106]	95	1			T524	3		T439	7		T498	6
values[107]	88	1			T524	6		T439	4		T498	3
values[108]	91	1			T524	1		T439	5		T498	5
values[109]	93	1			T524	4		T439	7		T498	6
values[110]	127	1			T524	2		T439	11		T498	5
values[111]	121	1			T524	3		T439	11		T498	4
values[112]	89	1			T524	7		T439	4		T498	7
values[113]	78	1			T524	5		T439	3		T498	4
values[114]	77	1			T524	4		T439	3		T498	4
values[115]	82	1			T524	1		T439	3		T498	4
values[116]	69	1			T524	5		T439	6		T498	2
values[117]	66	1			T524	6		T439	3		T498	4
values[118]	90	1			T524	6		T439	4		T498	5
values[119]	103	1			T524	8		T439	8		T498	2
values[120]	100	1			T524	6		T439	10		T498	5
values[121]	100	1			T524	3		T439	8		T498	9
values[122]	121	1			T524	5		T439	7		T498	10
values[123]	121	1			T524	7		T439	6		T498	13
values[124]	211	1			T524	17		T439	8		T498	25
values[125]	411	1			T524	31		T439	20		T498	42
values[126]	807	1			T524	56		T439	52		T498	50
values[127]	1926	1			T524	36		T439	30		T498	25
values[128]	3009	1			T524	6		T439	3		T498	2