Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	442	1			T117	4		T420	9		T524	1
all_values[1]	477	1			T117	2		T420	3		T524	2
all_values[2]	470	1			T117	3		T420	4		T527	1
all_values[3]	463	1			T117	4		T420	2		T528	1
all_values[4]	484	1			T117	3		T420	3		T438	1
all_values[5]	477	1			T117	1		T420	2		T528	1
all_values[6]	465	1			T117	1		T420	5		T528	1
all_values[7]	452	1			T117	3		T420	4		T438	2
all_values[8]	455	1			T117	2		T420	3		T519	1
all_values[9]	455	1			T117	4		T420	7		T400	5
all_values[10]	491	1			T420	6		T781	1		T524	1
all_values[11]	484	1			T117	1		T420	3		T528	1
all_values[12]	486	1			T117	3		T420	4		T438	2
all_values[13]	491	1			T117	3		T420	5		T400	4
all_values[14]	448	1			T117	1		T420	7		T527	1
all_values[15]	465	1			T117	2		T420	6		T519	1
all_values[16]	485	1			T117	2		T420	4		T438	2
all_values[17]	474	1			T117	1		T420	4		T519	1
all_values[18]	446	1			T117	1		T420	3		T519	1
all_values[19]	500	1			T117	7		T420	3		T519	1
all_values[20]	492	1			T117	1		T420	3		T438	4
all_values[21]	489	1			T117	2		T420	6		T527	1
all_values[22]	469	1			T117	2		T420	6		T438	2
all_values[23]	468	1			T117	4		T420	7		T438	2
all_values[24]	463	1			T117	2		T420	3		T528	1
all_values[25]	483	1			T117	2		T420	3		T438	1
all_values[26]	428	1			T117	2		T420	5		T438	2
all_values[27]	440	1			T420	8		T438	3		T524	1
all_values[28]	452	1			T117	1		T420	1		T438	3
all_values[29]	463	1			T420	3		T781	1		T524	1
all_values[30]	426	1			T117	3		T420	3		T528	1
all_values[31]	504	1			T117	2		T420	5		T438	1
all_values[32]	409	1			T117	1		T420	4		T438	1
all_values[33]	479	1			T117	2		T420	8		T519	1
all_values[34]	460	1			T117	3		T420	6		T527	1
all_values[35]	436	1			T420	4		T438	1		T400	1
all_values[36]	496	1			T117	4		T420	2		T438	3
all_values[37]	424	1			T117	1		T420	5		T438	3
all_values[38]	470	1			T117	5		T420	6		T438	3
all_values[39]	470	1			T117	2		T420	7		T400	5
all_values[40]	452	1			T117	3		T420	9		T528	1
all_values[41]	457	1			T420	3		T438	3		T521	1
all_values[42]	457	1			T117	1		T420	6		T438	1
all_values[43]	474	1			T117	2		T420	5		T527	1
all_values[44]	436	1			T117	3		T420	5		T527	1
all_values[45]	475	1			T117	1		T420	1		T438	3
all_values[46]	444	1			T117	2		T420	7		T524	1
all_values[47]	439	1			T117	1		T420	2		T527	1
all_values[48]	463	1			T117	3		T420	3		T521	1
all_values[49]	472	1			T117	2		T420	6		T438	4