Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3580	1			T73	1		T117	22		T420	46
all_values[1]	3655	1			T73	3		T117	15		T420	42
all_values[2]	3695	1			T73	1		T117	22		T420	52
all_values[3]	3613	1			T73	2		T117	17		T420	37
all_values[4]	3603	1			T73	6		T117	12		T420	31
all_values[5]	3695	1			T117	17		T420	29		T454	4
all_values[6]	3639	1			T73	4		T117	19		T420	44
all_values[7]	3601	1			T73	3		T117	20		T420	40
all_values[8]	3670	1			T73	1		T117	27		T420	55
all_values[9]	3568	1			T73	6		T117	16		T420	26
all_values[10]	3659	1			T73	4		T117	20		T420	29
all_values[11]	3656	1			T117	17		T420	45		T454	1
all_values[12]	3540	1			T73	2		T117	20		T420	46
all_values[13]	3608	1			T73	3		T117	13		T420	38
all_values[14]	3590	1			T73	3		T117	14		T420	40
all_values[15]	3623	1			T73	2		T117	16		T420	27
all_values[16]	3561	1			T73	3		T117	15		T420	35
all_values[17]	3719	1			T73	4		T117	14		T420	34
all_values[18]	3582	1			T73	4		T117	11		T420	33
all_values[19]	3558	1			T73	1		T117	22		T420	40
all_values[20]	3626	1			T73	3		T117	9		T420	39
all_values[21]	3606	1			T73	2		T117	20		T420	34
all_values[22]	3570	1			T73	3		T117	18		T420	38
all_values[23]	3566	1			T73	1		T117	15		T420	40
all_values[24]	3611	1			T73	6		T117	19		T420	31
all_values[25]	3670	1			T73	2		T117	15		T420	32
all_values[26]	3708	1			T73	5		T117	21		T420	44
all_values[27]	3614	1			T73	4		T117	12		T420	46
all_values[28]	3713	1			T117	22		T420	43		T454	1
all_values[29]	3669	1			T73	4		T117	14		T420	44
all_values[30]	3697	1			T73	6		T117	9		T420	47
all_values[31]	3604	1			T73	1		T117	18		T420	36
all_values[32]	3667	1			T73	3		T117	20		T420	40
all_values[33]	3619	1			T73	3		T117	28		T420	33
all_values[34]	3598	1			T73	6		T117	14		T420	38
all_values[35]	3662	1			T117	24		T420	27		T454	2
all_values[36]	3636	1			T73	4		T117	19		T420	36
all_values[37]	3661	1			T73	2		T117	26		T420	32
all_values[38]	3598	1			T73	5		T117	7		T420	47
all_values[39]	3531	1			T73	1		T117	15		T420	31
all_values[40]	3543	1			T73	3		T117	18		T420	44
all_values[41]	3563	1			T73	2		T117	13		T420	41
all_values[42]	3594	1			T73	2		T117	15		T420	42
all_values[43]	3621	1			T73	2		T117	20		T420	49
all_values[44]	3648	1			T73	2		T117	20		T420	31
all_values[45]	3658	1			T73	2		T117	22		T420	43
all_values[46]	3573	1			T73	4		T117	20		T420	44
all_values[47]	3648	1			T73	4		T117	13		T420	37
all_values[48]	3639	1			T73	3		T117	17		T420	35
all_values[49]	3673	1			T73	3		T117	12		T420	28
all_values[50]	3678	1			T73	3		T117	15		T420	32
all_values[51]	3578	1			T73	4		T117	11		T420	27
all_values[52]	3589	1			T73	3		T117	17		T420	39
all_values[53]	3592	1			T73	3		T117	16		T420	45
all_values[54]	3621	1			T73	3		T117	19		T420	40
all_values[55]	3584	1			T73	3		T117	13		T420	36
all_values[56]	3605	1			T73	2		T117	17		T420	22
all_values[57]	3527	1			T73	3		T117	16		T420	37
all_values[58]	3638	1			T73	4		T117	15		T420	35
all_values[59]	3651	1			T73	5		T117	22		T420	43
all_values[60]	3529	1			T73	3		T117	22		T420	35
all_values[61]	3593	1			T73	2		T117	30		T420	35
all_values[62]	3646	1			T73	2		T117	13		T420	39
all_values[63]	3650	1			T73	3		T117	19		T420	45