Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	147931	1			T77	35		T78	6		T79	181
values[2]	11573	1			T77	2		T79	4		T83	1
values[3]	4436	1			T239	33		T422	9		T521	1
values[4]	2591	1			T239	15		T422	4		T480	14
values[5]	1795	1			T239	16		T422	6		T480	3
values[6]	1321	1			T239	10		T422	5		T480	4
values[7]	951	1			T239	4		T422	4		T480	13
values[8]	763	1			T239	13		T422	3		T480	4
values[9]	610	1			T239	3		T422	1		T480	20
values[10]	571	1			T239	2		T422	6		T480	9
values[11]	514	1			T239	1		T422	7		T480	15
values[12]	426	1			T239	2		T422	1		T480	6
values[13]	468	1			T239	3		T422	2		T480	5
values[14]	448	1			T239	4		T422	2		T480	7
values[15]	424	1			T239	5		T422	2		T480	4
values[16]	445	1			T239	1		T422	1		T480	4
values[17]	431	1			T239	2		T422	1		T480	6
values[18]	437	1			T239	2		T422	1		T480	6
values[19]	477	1			T239	3		T422	4		T480	17
values[20]	405	1			T239	3		T422	1		T480	6
values[21]	497	1			T239	3		T422	1		T480	7
values[22]	455	1			T239	1		T422	1		T480	17
values[23]	424	1			T422	3		T480	10		T544	13
values[24]	383	1			T422	7		T480	5		T544	8
values[25]	410	1			T422	1		T480	4		T544	10
values[26]	397	1			T422	4		T480	6		T544	9
values[27]	398	1			T422	3		T480	4		T544	11
values[28]	454	1			T422	3		T480	7		T544	6
values[29]	434	1			T422	4		T480	12		T544	14
values[30]	408	1			T422	3		T480	5		T544	8
values[31]	382	1			T422	6		T480	3		T544	13
values[32]	375	1			T422	8		T480	9		T544	14
values[33]	375	1			T422	10		T480	11		T544	10
values[34]	444	1			T422	7		T480	17		T544	4
values[35]	385	1			T422	5		T480	4		T544	22
values[36]	418	1			T422	1		T480	3		T544	6
values[37]	409	1			T422	3		T480	11		T544	11
values[38]	458	1			T422	2		T480	8		T544	3
values[39]	389	1			T422	5		T480	5		T544	4
values[40]	432	1			T422	7		T480	4		T544	3
values[41]	423	1			T422	7		T480	7		T544	4
values[42]	470	1			T422	7		T480	13		T544	5
values[43]	373	1			T422	5		T480	3		T544	3
values[44]	370	1			T422	3		T480	8		T544	16
values[45]	386	1			T422	1		T480	11		T544	10
values[46]	391	1			T422	3		T480	11		T544	9
values[47]	428	1			T422	3		T480	6		T544	3
values[48]	423	1			T422	3		T480	8		T544	11
values[49]	366	1			T422	5		T480	9		T544	3
values[50]	361	1			T422	3		T480	6		T544	10
values[51]	378	1			T422	5		T480	3		T544	3
values[52]	350	1			T422	6		T480	2		T544	9
values[53]	375	1			T422	4		T480	3		T544	6
values[54]	329	1			T422	4		T480	8		T544	4
values[55]	381	1			T422	3		T480	2		T544	3
values[56]	384	1			T422	5		T480	3		T544	3
values[57]	345	1			T422	5		T544	9		T802	1
values[58]	301	1			T422	13		T544	6		T802	1
values[59]	343	1			T422	10		T544	11		T802	1
values[60]	356	1			T422	2		T544	13		T802	1
values[61]	274	1			T422	6		T544	6		T802	1
values[62]	279	1			T422	2		T544	5		T802	1
values[63]	272	1			T422	5		T544	7		T802	1
values[64]	297	1			T422	14		T544	11		T802	1
values[65]	254	1			T422	9		T544	12		T802	1
values[66]	232	1			T422	2		T544	2		T802	1
values[67]	192	1			T422	5		T802	1		T442	1
values[68]	215	1			T422	4		T802	1		T442	1
values[69]	237	1			T422	2		T802	1		T442	1
values[70]	192	1			T422	2		T802	1		T442	1
values[71]	160	1			T422	1		T802	1		T442	1
values[72]	174	1			T422	5		T802	1		T442	1
values[73]	159	1			T422	3		T802	1		T442	1
values[74]	138	1			T422	8		T802	1		T442	1
values[75]	152	1			T422	2		T802	1		T442	1
values[76]	114	1			T422	1		T802	1		T442	1
values[77]	125	1			T422	3		T802	1		T442	1
values[78]	146	1			T422	2		T802	1		T442	1
values[79]	109	1			T422	1		T802	1		T442	1
values[80]	91	1			T422	1		T802	1		T442	1
values[81]	110	1			T422	3		T802	1		T442	1
values[82]	114	1			T422	4		T802	1		T442	1
values[83]	112	1			T422	6		T802	1		T442	1
values[84]	108	1			T422	4		T802	1		T442	1
values[85]	102	1			T422	1		T802	1		T442	1
values[86]	114	1			T422	1		T802	1		T442	1
values[87]	117	1			T422	3		T802	1		T442	1
values[88]	116	1			T422	2		T802	1		T442	1
values[89]	104	1			T422	1		T802	2		T442	1
values[90]	133	1			T422	3		T802	3		T442	1
values[91]	105	1			T422	4		T802	5		T442	1
values[92]	101	1			T422	5		T802	3		T442	1
values[93]	112	1			T422	5		T802	4		T442	1
values[94]	106	1			T422	1		T802	1		T442	1
values[95]	94	1			T422	1		T802	1		T442	1
values[96]	101	1			T422	9		T802	1		T442	1
values[97]	111	1			T422	9		T802	3		T442	1
values[98]	99	1			T422	7		T802	3		T442	1
values[99]	110	1			T422	6		T802	2		T442	1
values[100]	97	1			T422	6		T802	3		T442	1
values[101]	102	1			T422	3		T802	7		T442	1
values[102]	115	1			T422	5		T802	2		T442	1
values[103]	106	1			T422	3		T802	7		T442	1
values[104]	88	1			T422	5		T802	2		T442	1
values[105]	87	1			T422	2		T802	3		T442	1
values[106]	89	1			T422	4		T802	3		T442	1
values[107]	106	1			T422	6		T802	2		T442	1
values[108]	85	1			T422	3		T802	1		T442	1
values[109]	88	1			T422	4		T802	2		T442	1
values[110]	89	1			T422	7		T802	1		T442	1
values[111]	111	1			T422	11		T802	2		T442	1
values[112]	97	1			T422	6		T802	2		T442	1
values[113]	75	1			T422	2		T802	2		T442	1
values[114]	81	1			T422	2		T802	1		T442	1
values[115]	84	1			T422	4		T802	2		T442	1
values[116]	80	1			T422	4		T802	1		T442	1
values[117]	69	1			T802	1		T442	1		T834	3
values[118]	94	1			T802	6		T442	1		T834	3
values[119]	79	1			T802	1		T442	1		T834	2
values[120]	74	1			T802	1		T442	4		T834	1
values[121]	62	1			T802	1		T442	5		T834	2
values[122]	79	1			T802	1		T442	1		T834	2
values[123]	54	1			T802	1		T442	1		T834	1
values[124]	74	1			T802	2		T442	1		T834	1
values[125]	70	1			T802	1		T442	1		T834	2
values[126]	146	1			T802	2		T442	4		T834	3
values[127]	844	1			T802	39		T442	36		T834	28
values[128]	6714	1			T802	330		T442	369		T834	244