Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	95.46	93.77	95.25		94.47	97.53	99.58

Total tests in report: 2877

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.67	39.67	43.80	43.80	44.05	44.05	30.79	30.79			57.51	57.51	58.74	58.74	3.14	3.14	/workspace/coverage/default/2.chip_sw_alert_test.3345127916
49.05	9.38	49.42	5.62	58.10	14.06	31.08	0.29			68.24	10.73	83.92	25.17	3.57	0.43	/workspace/coverage/cover_reg_top/9.chip_csr_rw.3700782371
56.28	7.23	64.22	14.81	67.88	9.78	35.80	4.71			81.78	13.54	84.44	0.52	3.57	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3255757005
61.89	5.61	76.15	11.92	70.93	3.05	43.01	7.21			82.38	0.60	84.44	0.00	14.45	10.88	/workspace/coverage/cover_reg_top/82.xbar_stress_all.4233286664
66.44	4.55	76.15	0.00	70.93	0.00	43.01	0.00			82.38	0.00	84.44	0.00	41.72	27.27	/workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1770522416
69.92	3.48	82.22	6.07	75.30	4.37	46.93	3.93			84.37	1.99	88.99	4.55	41.72	0.00	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1000849064
73.40	3.48	82.22	0.00	75.55	0.25	46.93	0.00			84.46	0.10	88.99	0.00	62.25	20.53	/workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3224577636
76.48	3.08	82.22	0.00	75.56	0.01	65.03	18.10			84.47	0.01	89.34	0.35	62.26	0.01	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.857123280
78.71	2.23	82.22	0.00	75.96	0.40	65.03	0.00			84.60	0.13	89.34	0.00	75.13	12.87	/workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.728157309
80.37	1.66	82.51	0.29	76.11	0.15	74.01	8.98			84.78	0.18	89.69	0.35	75.13	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.309208433
81.66	1.29	82.51	0.00	76.21	0.11	74.01	0.00			84.78	0.00	89.69	0.00	82.74	7.61	/workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.850041209
82.76	1.10	83.92	1.40	78.78	2.57	74.15	0.13			87.27	2.49	89.69	0.00	82.74	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3789747234
83.76	1.01	83.92	0.00	78.78	0.00	80.19	6.04			87.27	0.00	89.69	0.00	82.74	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2237779102
84.72	0.95	85.24	1.32	79.90	1.12	80.61	0.42			88.56	1.29	91.26	1.57	82.74	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.518793059
85.56	0.85	85.97	0.73	80.13	0.23	80.62	0.01			88.81	0.25	95.10	3.85	82.74	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1076212065
86.36	0.80	87.59	1.63	81.18	1.05	81.70	1.07			89.69	0.88	95.28	0.17	82.74	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2012445217
87.15	0.79	89.40	1.81	82.39	1.21	82.47	0.78			90.64	0.95	95.28	0.00	82.74	0.00	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2709439187
87.92	0.77	89.40	0.00	82.39	0.00	82.47	0.00			90.64	0.00	95.28	0.00	87.35	4.61	/workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3365905178
88.66	0.74	90.68	1.28	83.44	1.05	83.34	0.87			91.88	1.24	95.28	0.00	87.35	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.2176045761
89.25	0.59	90.69	0.01	86.33	2.89	83.54	0.20			91.90	0.02	95.28	0.00	87.76	0.41	/workspace/coverage/cover_reg_top/8.chip_tl_errors.3085759955
89.81	0.56	90.69	0.00	86.37	0.04	83.54	0.00			91.92	0.02	95.28	0.00	91.04	3.28	/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3209672517
90.32	0.52	90.69	0.01	86.64	0.27	84.04	0.50			91.93	0.01	95.28	0.00	93.36	2.33	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.2014527663
90.81	0.49	91.75	1.06	86.94	0.30	84.76	0.71			92.09	0.16	95.98	0.70	93.36	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2904822747
91.29	0.48	92.37	0.62	88.88	1.94	84.85	0.10			92.28	0.19	95.98	0.00	93.36	0.00	/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1928093997
91.69	0.40	92.48	0.11	88.92	0.05	87.07	2.21			92.31	0.02	95.98	0.00	93.36	0.00	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.375334518
92.03	0.35	93.00	0.51	89.37	0.44	87.73	0.66			92.77	0.46	95.98	0.00	93.36	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.1774175814
92.34	0.31	93.00	0.00	89.37	0.00	87.73	0.00			92.77	0.00	95.98	0.00	95.22	1.86	/workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3561710566
92.60	0.26	93.32	0.32	89.53	0.16	88.66	0.93			92.87	0.10	95.98	0.00	95.26	0.05	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1572135961
92.86	0.26	93.32	0.00	89.61	0.08	88.67	0.01			92.87	0.00	95.98	0.00	96.71	1.45	/workspace/coverage/cover_reg_top/3.xbar_random_large_delays.3835779958
93.10	0.24	93.32	0.00	89.61	0.00	90.13	1.46			92.87	0.00	95.98	0.00	96.71	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1538278579
93.31	0.21	93.41	0.09	89.81	0.20	91.00	0.88			92.95	0.08	95.98	0.00	96.71	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.1070151465
93.49	0.18	93.62	0.21	89.97	0.16	91.22	0.22			93.10	0.15	96.33	0.35	96.71	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1615141264
93.64	0.15	93.82	0.21	90.29	0.32	91.57	0.36			93.10	0.00	96.33	0.00	96.71	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1678041662
93.77	0.14	93.82	0.00	90.36	0.07	91.57	0.00			93.13	0.03	96.33	0.00	97.43	0.72	/workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.4128530639
93.90	0.13	93.83	0.01	90.72	0.36	91.58	0.01			93.53	0.41	96.33	0.00	97.43	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3446945893
94.01	0.11	93.87	0.04	90.85	0.13	91.79	0.21			93.62	0.09	96.50	0.17	97.43	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.194521061
94.11	0.10	93.87	0.00	91.07	0.22	91.79	0.00			93.63	0.01	96.50	0.00	97.80	0.38	/workspace/coverage/cover_reg_top/39.xbar_stress_all.3958818583
94.21	0.10	93.93	0.06	91.07	0.00	92.31	0.53			93.64	0.01	96.50	0.00	97.81	0.01	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1554599485
94.31	0.09	94.12	0.19	91.28	0.22	92.31	0.00			93.80	0.16	96.50	0.00	97.81	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.387003795
94.38	0.07	94.12	0.00	91.29	0.01	92.74	0.43			93.80	0.00	96.50	0.00	97.81	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1079476446
94.45	0.07	94.12	0.00	91.71	0.43	92.74	0.00			93.80	0.00	96.50	0.00	97.81	0.00	/workspace/coverage/cover_reg_top/14.chip_tl_errors.3576787504
94.52	0.07	94.12	0.00	91.71	0.00	93.15	0.41			93.80	0.00	96.50	0.00	97.81	0.00	/workspace/coverage/default/1.chip_sw_edn_auto_mode.2781681440
94.58	0.06	94.12	0.01	91.88	0.17	93.15	0.01			94.00	0.19	96.50	0.00	97.81	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3846515489
94.64	0.06	94.19	0.08	91.93	0.04	93.36	0.21			94.01	0.02	96.50	0.00	97.83	0.01	/workspace/coverage/default/81.chip_sw_all_escalation_resets.2079227965
94.69	0.06	94.19	0.00	91.98	0.05	93.36	0.00			94.01	0.00	96.50	0.00	98.12	0.29	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.3209603624
94.74	0.05	94.23	0.03	92.00	0.02	93.36	0.01			94.04	0.03	96.68	0.17	98.13	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.207988989
94.79	0.05	94.23	0.00	92.02	0.01	93.62	0.25			94.05	0.01	96.68	0.00	98.13	0.00	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1479010751
94.83	0.04	94.25	0.02	92.03	0.02	93.82	0.21			94.06	0.01	96.68	0.00	98.13	0.00	/workspace/coverage/cover_reg_top/33.xbar_random.1318077054
94.87	0.04	94.25	0.00	92.03	0.00	94.07	0.25			94.06	0.00	96.68	0.00	98.13	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.196603904
94.91	0.04	94.26	0.01	92.05	0.01	94.08	0.01			94.09	0.02	96.85	0.17	98.14	0.01	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2653114767
94.95	0.04	94.27	0.01	92.07	0.02	94.09	0.01			94.10	0.02	97.03	0.17	98.16	0.01	/workspace/coverage/default/59.chip_sw_all_escalation_resets.3464917451
94.99	0.04	94.31	0.04	92.12	0.05	94.16	0.07			94.15	0.05	97.03	0.00	98.16	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4107267083
95.02	0.04	94.32	0.01	92.14	0.02	94.16	0.00			94.16	0.01	97.20	0.17	98.17	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.2932321952
95.06	0.04	94.32	0.01	92.15	0.01	94.17	0.01			94.17	0.01	97.38	0.17	98.18	0.01	/workspace/coverage/default/89.chip_sw_all_escalation_resets.1947249769
95.09	0.03	94.34	0.02	92.18	0.04	94.26	0.09			94.21	0.04	97.38	0.00	98.18	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3936065740
95.12	0.03	94.34	0.00	92.18	0.00	94.26	0.01			94.21	0.00	97.55	0.17	98.18	0.00	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.658669603
95.15	0.03	94.41	0.07	92.19	0.01	94.35	0.09			94.22	0.01	97.55	0.00	98.18	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.3177911471
95.18	0.03	94.49	0.07	92.22	0.03	94.36	0.01			94.26	0.05	97.55	0.00	98.18	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1743262258
95.20	0.03	94.49	0.00	92.22	0.01	94.36	0.00			94.26	0.00	97.55	0.00	98.33	0.15	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1848722426
95.23	0.03	94.49	0.00	92.38	0.16	94.36	0.00			94.26	0.00	97.55	0.00	98.33	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.338240217
95.25	0.02	94.49	0.00	92.52	0.15	94.36	0.00			94.26	0.00	97.55	0.00	98.33	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.2336654143
95.28	0.02	94.56	0.08	92.57	0.05	94.36	0.00			94.28	0.02	97.55	0.00	98.33	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1358396480
95.30	0.02	94.56	0.00	92.57	0.00	94.50	0.14			94.28	0.00	97.55	0.00	98.33	0.00	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3108266823
95.32	0.02	94.63	0.07	92.62	0.05	94.50	0.00			94.30	0.02	97.55	0.00	98.33	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.4191456335
95.34	0.02	94.66	0.03	92.67	0.05	94.51	0.02			94.32	0.02	97.55	0.00	98.33	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.705601476
95.36	0.02	94.66	0.00	92.74	0.07	94.51	0.00			94.34	0.02	97.55	0.00	98.36	0.02	/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1981321632
95.38	0.02	94.66	0.00	92.74	0.00	94.62	0.11			94.34	0.00	97.55	0.00	98.36	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1930553388
95.39	0.02	94.67	0.01	92.77	0.04	94.66	0.04			94.35	0.02	97.55	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2935282687
95.41	0.02	94.67	0.00	92.79	0.01	94.66	0.00			94.35	0.00	97.55	0.00	98.44	0.08	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.262965295
95.43	0.01	94.67	0.00	92.88	0.09	94.66	0.00			94.35	0.00	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.4010092810
95.44	0.01	94.67	0.00	92.96	0.08	94.66	0.00			94.35	0.00	97.55	0.00	98.44	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.949393141
95.45	0.01	94.67	0.00	92.97	0.01	94.66	0.00			94.35	0.00	97.55	0.00	98.51	0.07	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.775927797
95.47	0.01	94.70	0.02	92.99	0.02	94.69	0.03			94.35	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1206319748
95.48	0.01	94.72	0.02	93.00	0.01	94.72	0.03			94.37	0.02	97.55	0.00	98.51	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1507760446
95.49	0.01	94.72	0.00	93.07	0.07	94.72	0.00			94.37	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.2367512616
95.50	0.01	94.74	0.02	93.08	0.01	94.75	0.04			94.37	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3424240336
95.51	0.01	94.74	0.00	93.10	0.02	94.75	0.00			94.39	0.02	97.55	0.00	98.53	0.02	/workspace/coverage/cover_reg_top/22.xbar_stress_all.301984590
95.52	0.01	94.75	0.01	93.10	0.00	94.81	0.06			94.39	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2999986028
95.53	0.01	94.78	0.03	93.12	0.02	94.82	0.01			94.39	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.223181264
95.54	0.01	94.78	0.00	93.17	0.05	94.82	0.00			94.39	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/cover_reg_top/36.xbar_access_same_device.3507206664
95.55	0.01	94.78	0.00	93.23	0.05	94.82	0.00			94.39	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3838776861
95.56	0.01	94.78	0.00	93.23	0.00	94.87	0.05			94.39	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.453523797
95.57	0.01	94.78	0.00	93.23	0.00	94.92	0.05			94.39	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.971718726
95.57	0.01	94.79	0.01	93.25	0.03	94.92	0.00			94.39	0.01	97.55	0.00	98.53	0.00	/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1821414475
95.58	0.01	94.81	0.02	93.26	0.01	94.93	0.01			94.41	0.02	97.55	0.00	98.53	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1378424562
95.59	0.01	94.81	0.00	93.26	0.00	94.93	0.00			94.41	0.00	97.55	0.00	98.58	0.05	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2118347535
95.60	0.01	94.81	0.00	93.26	0.00	94.93	0.00			94.41	0.00	97.55	0.00	98.63	0.05	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2238211594
95.61	0.01	94.83	0.02	93.27	0.01	94.93	0.01			94.43	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2780150360
95.61	0.01	94.83	0.00	93.30	0.03	94.93	0.00			94.43	0.00	97.55	0.00	98.64	0.01	/workspace/coverage/cover_reg_top/15.chip_tl_errors.2621225822
95.62	0.01	94.83	0.00	93.33	0.03	94.93	0.00			94.43	0.01	97.55	0.00	98.64	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3805354577
95.63	0.01	94.83	0.00	93.37	0.04	94.93	0.00			94.43	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.1142344153
95.63	0.01	94.83	0.00	93.37	0.00	94.93	0.00			94.43	0.00	97.55	0.00	98.67	0.04	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.400966882
95.64	0.01	94.83	0.00	93.37	0.00	94.93	0.00			94.43	0.00	97.55	0.00	98.71	0.04	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2632154778
95.64	0.01	94.83	0.00	93.39	0.01	94.95	0.02			94.43	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2610783188
95.65	0.01	94.83	0.00	93.39	0.01	94.98	0.03			94.43	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2686379142
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95.67	0.01	94.83	0.00	93.44	0.00	95.04	0.03			94.43	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3381821948
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95.68	0.01	94.83	0.00	93.53	0.02	95.04	0.00			94.43	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1684801070
95.69	0.01	94.83	0.00	93.53	0.00	95.04	0.00			94.43	0.00	97.55	0.00	98.74	0.02	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2139643807
95.69	0.01	94.83	0.00	93.53	0.00	95.04	0.00			94.43	0.00	97.55	0.00	98.77	0.02	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3926557533
95.70	0.01	94.83	0.00	93.53	0.00	95.07	0.02			94.43	0.00	97.55	0.00	98.77	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2931996370
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95.71	0.01	94.83	0.00	93.58	0.02	95.07	0.00			94.43	0.00	97.55	0.00	98.77	0.00	/workspace/coverage/default/2.chip_sw_gpio.572058749
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95.71	0.01	94.85	0.02	93.58	0.00	95.09	0.00			94.43	0.00	97.55	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.2942203789
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95.72	0.01	94.85	0.00	93.59	0.01	95.09	0.00			94.45	0.00	97.55	0.00	98.78	0.01	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.3586389243
95.72	0.01	94.85	0.00	93.59	0.00	95.11	0.02			94.45	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1852261359
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95.73	0.01	94.87	0.00	93.60	0.00	95.12	0.01			94.45	0.00	97.55	0.00	98.79	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.3233792994
95.73	0.01	94.87	0.00	93.60	0.00	95.14	0.02			94.45	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.873248822
95.73	0.01	94.87	0.00	93.60	0.01	95.14	0.00			94.45	0.00	97.55	0.00	98.80	0.01	/workspace/coverage/default/40.chip_sw_all_escalation_resets.2238035204
95.74	0.01	94.87	0.00	93.61	0.01	95.14	0.00			94.45	0.00	97.55	0.00	98.80	0.00	/workspace/coverage/cover_reg_top/41.xbar_stress_all.863810998
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95.74	0.01	94.87	0.00	93.64	0.01	95.14	0.00			94.45	0.00	97.55	0.00	98.80	0.00	/workspace/coverage/default/1.chip_sw_gpio.3644731517
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95.75	0.01	94.87	0.00	93.66	0.00	95.14	0.01			94.45	0.00	97.55	0.00	98.81	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.3973534431
95.75	0.01	94.87	0.00	93.66	0.01	95.15	0.01			94.45	0.00	97.55	0.00	98.81	0.00	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2560507834
95.75	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.83	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2904564960
95.75	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.84	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.856872546
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95.76	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.86	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.4026304804
95.76	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.87	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.577174835
95.76	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.88	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3316464078
95.76	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.90	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.3772573395
95.76	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.91	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2215924474
95.77	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.92	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.4078158044
95.77	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.93	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2848302408
95.77	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.94	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1634079063
95.77	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.95	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3890638269
95.77	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.97	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3334428684
95.78	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.98	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.1804093688
95.78	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	98.99	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3413650997
95.78	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.3041659165
95.78	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.01	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1008405725
95.78	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.02	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1426855432
95.79	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.04	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.1271612727
95.79	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.05	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.717811091
95.79	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.06	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.665742241
95.79	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.07	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1478243465
95.79	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.08	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115619205
95.80	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.964409436
95.80	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.138885689
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95.80	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.662434031
95.80	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.14	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3837788354
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95.81	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.17	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.341417336
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95.86	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.47	0.01	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1393736048
95.86	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.48	0.01	/workspace/coverage/default/7.chip_sw_all_escalation_resets.2233320993
95.86	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1478432860
95.86	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/70.chip_sw_all_escalation_resets.4263333350
95.87	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2790158534
95.87	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/8.chip_sw_all_escalation_resets.880441451
95.87	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2283588738
95.87	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.574074733
95.87	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3438496580
95.88	0.01	94.87	0.00	93.66	0.00	95.15	0.00			94.45	0.00	97.55	0.00	99.58	0.01	/workspace/coverage/default/90.chip_sw_all_escalation_resets.2443314298
95.88	0.01	94.87	0.00	93.67	0.01	95.15	0.01			94.45	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2835363336
95.88	0.01	94.87	0.00	93.68	0.01	95.15	0.00			94.45	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.541626454
95.88	0.01	94.87	0.00	93.69	0.01	95.15	0.00			94.45	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2952723697
95.88	0.01	94.87	0.00	93.70	0.01	95.15	0.00			94.45	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.2275048608
95.88	0.01	94.87	0.01	93.70	0.00	95.16	0.01			94.45	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3522811118
95.89	0.01	94.88	0.01	93.70	0.01	95.16	0.00			94.45	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.341973563
95.89	0.01	94.88	0.00	93.70	0.00	95.17	0.01			94.45	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.4868362
95.89	0.01	94.88	0.00	93.70	0.00	95.18	0.01			94.45	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.4285931940
95.89	0.01	94.88	0.00	93.70	0.00	95.19	0.01			94.45	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3323682120
95.89	0.01	94.88	0.00	93.70	0.00	95.20	0.01			94.45	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.3791929928
95.89	0.01	94.88	0.00	93.70	0.00	95.20	0.00			94.46	0.01	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2934840010
95.90	0.01	94.88	0.00	93.70	0.00	95.20	0.00			94.47	0.01	97.55	0.00	99.58	0.00	/workspace/coverage/default/4.chip_tap_straps_dev.3116111462
95.90	0.01	94.88	0.00	93.71	0.01	95.20	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_rw.652916807
95.90	0.01	94.88	0.00	93.72	0.01	95.20	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.521027276
95.90	0.01	94.88	0.00	93.72	0.01	95.20	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2941057403
95.90	0.01	94.88	0.00	93.73	0.01	95.20	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4288352128
95.90	0.01	94.88	0.00	93.74	0.01	95.20	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.454408293
95.90	0.01	94.88	0.00	93.74	0.00	95.20	0.01			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1253806959
95.90	0.01	94.88	0.00	93.74	0.00	95.21	0.01			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1781231503
95.90	0.01	94.88	0.01	93.74	0.00	95.21	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1289676580
95.91	0.01	94.88	0.00	93.74	0.00	95.22	0.01			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1687656727
95.91	0.01	94.88	0.00	93.74	0.00	95.22	0.01			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.930534062
95.91	0.01	94.88	0.00	93.74	0.00	95.22	0.01			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2764102972
95.91	0.01	94.88	0.00	93.74	0.00	95.23	0.01			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3302998725
95.91	0.01	94.88	0.00	93.74	0.01	95.23	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.3990381944
95.91	0.01	94.88	0.00	93.75	0.01	95.23	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1039876126
95.91	0.01	94.88	0.00	93.75	0.01	95.23	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.995723422
95.91	0.01	94.88	0.00	93.75	0.01	95.23	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1861061171
95.91	0.01	94.88	0.00	93.76	0.01	95.23	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.3938146655
95.91	0.01	94.88	0.00	93.76	0.01	95.23	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/98.xbar_error_random.2196430611
95.91	0.01	94.88	0.00	93.76	0.01	95.23	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_irq.3684977698
95.91	0.01	94.88	0.00	93.77	0.01	95.23	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.13811945
95.91	0.01	94.88	0.00	93.77	0.00	95.23	0.01			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_tap_straps_rma.2267533085
95.91	0.01	94.89	0.01	93.77	0.00	95.23	0.00			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_pattgen_ios.1013156678
95.91	0.01	94.89	0.00	93.77	0.00	95.24	0.01			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4230204632
95.91	0.01	94.89	0.00	93.77	0.00	95.24	0.01			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3512660722
95.91	0.01	94.89	0.00	93.77	0.00	95.24	0.01			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2299601093
95.92	0.01	94.89	0.00	93.77	0.00	95.24	0.01			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2019751664
95.92	0.01	94.89	0.00	93.77	0.00	95.24	0.01			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3252439331
95.92	0.01	94.89	0.00	93.77	0.00	95.25	0.01			94.47	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.868010568

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1912055971
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3377819085
/workspace/coverage/cover_reg_top/0.chip_csr_rw.4115435401
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3577471647
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1992458816
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2577626646
/workspace/coverage/cover_reg_top/0.chip_tl_errors.2218417567
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2594522587
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1318982659
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2665067831
/workspace/coverage/cover_reg_top/0.xbar_error_random.1548603614
/workspace/coverage/cover_reg_top/0.xbar_random.1347298302
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3337899643
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1531449535
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.4231573677
/workspace/coverage/cover_reg_top/0.xbar_same_source.32257924
/workspace/coverage/cover_reg_top/0.xbar_smoke.257978420
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.699004297
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1303355510
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3988797329
/workspace/coverage/cover_reg_top/0.xbar_stress_all.4241646106
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3050948736
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1833786149
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3313772674
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1134999446
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3217754668
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.819602427
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2345182503
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2383869375
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.461140098
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.3071745229
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3489080382
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.200905935
/workspace/coverage/cover_reg_top/1.xbar_error_random.36687725
/workspace/coverage/cover_reg_top/1.xbar_random.345698170
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2037570372
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.4052687355
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3552422635
/workspace/coverage/cover_reg_top/1.xbar_same_source.2448119367
/workspace/coverage/cover_reg_top/1.xbar_smoke.2922341070
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1175008689
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1686316714
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3476030131
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3472733267
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.403950554
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1173444733
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2995626536
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.4071691893
/workspace/coverage/cover_reg_top/10.chip_csr_rw.107672350
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.709074577
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3092663672
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2415879518
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1505355529
/workspace/coverage/cover_reg_top/10.xbar_error_random.3750912556
/workspace/coverage/cover_reg_top/10.xbar_random.3753746756
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2768563992
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.254549297
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2054397109
/workspace/coverage/cover_reg_top/10.xbar_same_source.3551675239
/workspace/coverage/cover_reg_top/10.xbar_smoke.936610043
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3207296746
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.387966911
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2854937785
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1610918630
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2039584274
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1324628512
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.778709680
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.754392791
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3757993979
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.213354967
/workspace/coverage/cover_reg_top/11.chip_tl_errors.989955327
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.954484978
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3244942221
/workspace/coverage/cover_reg_top/11.xbar_error_random.2735121160
/workspace/coverage/cover_reg_top/11.xbar_random.1064363997
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.4246409549
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.655769507
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2503325431
/workspace/coverage/cover_reg_top/11.xbar_same_source.3157202899
/workspace/coverage/cover_reg_top/11.xbar_smoke.279986689
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2046873296
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.394709349
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4041023997
/workspace/coverage/cover_reg_top/11.xbar_stress_all.4179809691
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.4197371119
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3842984537
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3659914
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.647919525
/workspace/coverage/cover_reg_top/12.chip_csr_rw.604054936
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2305850678
/workspace/coverage/cover_reg_top/12.chip_tl_errors.718787516
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.4104756527
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3832823027
/workspace/coverage/cover_reg_top/12.xbar_error_random.3059635043
/workspace/coverage/cover_reg_top/12.xbar_random.1340741396
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.190064732
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.4077516012
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1814316117
/workspace/coverage/cover_reg_top/12.xbar_same_source.3106902091
/workspace/coverage/cover_reg_top/12.xbar_smoke.1584478673
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1673653185
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.69878541
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1317824662
/workspace/coverage/cover_reg_top/12.xbar_stress_all.337476311
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1818456161
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1113208014
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3300438490
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.868035915
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2109503194
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3082985217
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.566973852
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1516844593
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3084424402
/workspace/coverage/cover_reg_top/13.xbar_error_random.1642047660
/workspace/coverage/cover_reg_top/13.xbar_random.2978836845
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3475621540
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1703997636
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3815005984
/workspace/coverage/cover_reg_top/13.xbar_same_source.1018342040
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/workspace/coverage/default/2.rom_e2e_asm_init_rma.2150019623
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2603712793
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1857326614
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.899086897
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.353731647
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/workspace/coverage/default/2.rom_e2e_shutdown_output.1844595631
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/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1966623700
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3326715491
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/workspace/coverage/default/3.chip_sw_uart_tx_rx.2700897803
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3344988118
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/workspace/coverage/default/3.chip_tap_straps_testunlock0.627586040
/workspace/coverage/default/30.chip_sw_all_escalation_resets.2479044177
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1938082883
/workspace/coverage/default/32.chip_sw_all_escalation_resets.477942676
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072711359
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1069113284
/workspace/coverage/default/34.chip_sw_all_escalation_resets.993702090
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.693244415
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2322792954
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2826712235
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1929459142
/workspace/coverage/default/38.chip_sw_all_escalation_resets.418685872
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1977055330
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1044367804
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1740633773
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2740723118
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.603965837
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2579604007
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1404773489
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.192937109
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2917181982
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2015639536
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1806967167
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1211270751
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1388103025
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2758212890
/workspace/coverage/default/4.chip_tap_straps_prod.161532755
/workspace/coverage/default/4.chip_tap_straps_rma.620745348
/workspace/coverage/default/4.chip_tap_straps_testunlock0.1201562996
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1310247059
/workspace/coverage/default/43.chip_sw_all_escalation_resets.4053456243
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1836812310
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119592798
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3123426046
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.459392976
/workspace/coverage/default/46.chip_sw_all_escalation_resets.4041947803
/workspace/coverage/default/47.chip_sw_all_escalation_resets.1127388745
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.639616173
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3695707650
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2206043000
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3321174439
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.548423767
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.968491016
/workspace/coverage/default/50.chip_sw_all_escalation_resets.255049264
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1262509774
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1536822133
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2087441151
/workspace/coverage/default/52.chip_sw_all_escalation_resets.246092758
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3975706535
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1847139374
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.571685186
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2734766511
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3799658231
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1871410141
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1781422350
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1268092005
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2958343640
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3328628585
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1997086282
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2882626556
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.734581468
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4125634192
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.828486805
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2805100152
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1599664333
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.40042039
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2438013691
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1709551933
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3633165315
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1164008498
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3600644706
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3352838041
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2261899274
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3140707794
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.4025962906
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3898371736
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1487200101
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1634832964
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2392090399
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1229192695
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4029155943
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3105135463
/workspace/coverage/default/71.chip_sw_all_escalation_resets.415018851
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2952838774
/workspace/coverage/default/72.chip_sw_all_escalation_resets.4247061283
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1149241049
/workspace/coverage/default/73.chip_sw_all_escalation_resets.884056478
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.980502574
/workspace/coverage/default/74.chip_sw_all_escalation_resets.3932948587
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2042567823
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3515938087
/workspace/coverage/default/76.chip_sw_all_escalation_resets.791363276
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.906960428
/workspace/coverage/default/77.chip_sw_all_escalation_resets.4063834294
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.592375352
/workspace/coverage/default/78.chip_sw_all_escalation_resets.4207087923
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3165213207
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3959828277
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.786288645
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2024143158
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1491080718
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3731917985
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2228412737
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1044086949
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2975425534
/workspace/coverage/default/82.chip_sw_all_escalation_resets.359249300
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2155543198
/workspace/coverage/default/83.chip_sw_all_escalation_resets.629089759
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1176930498
/workspace/coverage/default/84.chip_sw_all_escalation_resets.871830269
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3321427097
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2229967059
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3194797763
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1112335752
/workspace/coverage/default/87.chip_sw_all_escalation_resets.752133159
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3251382615
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1292594749
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.283578546
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1103075259
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.223199026
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3970688943
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1007910720
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1739170188
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2706944541
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1792200146
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2769271526
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2322553195
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2419608156
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3840245946
/workspace/coverage/default/98.chip_sw_all_escalation_resets.523784982
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2746117978
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3362211285
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3107679361
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1937758927
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1249374038
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.736990278
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2676152179
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.555498105
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2898827286

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Total test records in report: 2877

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2100054685			Jun 30 07:41:11 PM PDT 24	Jun 30 07:59:47 PM PDT 24	5464339164 ps
T5	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.157784039			Jun 30 08:00:47 PM PDT 24	Jun 30 08:11:26 PM PDT 24	3947262650 ps
T6	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3649402406			Jun 30 07:53:14 PM PDT 24	Jun 30 07:55:18 PM PDT 24	2099950097 ps
T17	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1507760446			Jun 30 07:56:44 PM PDT 24	Jun 30 08:11:26 PM PDT 24	6613041720 ps
T62	/workspace/coverage/default/2.chip_sw_alert_test.3345127916			Jun 30 07:55:33 PM PDT 24	Jun 30 08:00:56 PM PDT 24	3053776472 ps
T20	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3108266823			Jun 30 07:51:14 PM PDT 24	Jun 30 07:53:52 PM PDT 24	3354189767 ps
T18	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.210677493			Jun 30 07:29:35 PM PDT 24	Jun 30 07:35:05 PM PDT 24	3632833782 ps
T19	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2802434735			Jun 30 07:30:09 PM PDT 24	Jun 30 07:38:33 PM PDT 24	4576800434 ps
T45	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.375334518			Jun 30 07:55:03 PM PDT 24	Jun 30 08:16:08 PM PDT 24	7445809714 ps
T21	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.857123280			Jun 30 07:30:48 PM PDT 24	Jun 30 07:39:49 PM PDT 24	5454227128 ps
T150	/workspace/coverage/default/1.chip_plic_all_irqs_10.1774175814			Jun 30 07:46:59 PM PDT 24	Jun 30 07:56:42 PM PDT 24	3390480400 ps
T123	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2653114767			Jun 30 08:06:15 PM PDT 24	Jun 30 08:13:56 PM PDT 24	3442041820 ps
T60	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.306312753			Jun 30 07:32:59 PM PDT 24	Jun 30 07:44:11 PM PDT 24	4280960972 ps
T338	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3328628585			Jun 30 08:07:55 PM PDT 24	Jun 30 08:15:41 PM PDT 24	3980298056 ps
T29	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2709439187			Jun 30 07:38:50 PM PDT 24	Jun 30 07:42:24 PM PDT 24	3398228185 ps
T246	/workspace/coverage/default/1.chip_plic_all_irqs_0.3255757005			Jun 30 07:46:38 PM PDT 24	Jun 30 08:10:40 PM PDT 24	6304134906 ps
T66	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3148776459			Jun 30 07:42:52 PM PDT 24	Jun 30 08:13:18 PM PDT 24	18843734632 ps
T355	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.13811945			Jun 30 07:29:03 PM PDT 24	Jun 30 07:44:45 PM PDT 24	4758882680 ps
T22	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.309208433			Jun 30 07:43:50 PM PDT 24	Jun 30 09:17:04 PM PDT 24	45060789396 ps
T67	/workspace/coverage/default/97.chip_sw_all_escalation_resets.3840245946			Jun 30 08:11:20 PM PDT 24	Jun 30 08:25:08 PM PDT 24	5645348440 ps
T157	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2771627267			Jun 30 07:32:23 PM PDT 24	Jun 30 07:34:05 PM PDT 24	2066318592 ps
T68	/workspace/coverage/default/80.chip_sw_all_escalation_resets.2228412737			Jun 30 08:09:53 PM PDT 24	Jun 30 08:19:13 PM PDT 24	4358702268 ps
T115	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1206319748			Jun 30 08:00:00 PM PDT 24	Jun 30 08:44:04 PM PDT 24	13060340776 ps
T208	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4071774642			Jun 30 07:51:23 PM PDT 24	Jun 30 08:11:28 PM PDT 24	5543530380 ps
T112	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3729026307			Jun 30 07:55:28 PM PDT 24	Jun 30 08:00:17 PM PDT 24	3537195911 ps
T84	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1572135961			Jun 30 07:45:16 PM PDT 24	Jun 30 08:05:08 PM PDT 24	11550636680 ps
T294	/workspace/coverage/default/1.chip_sival_flash_info_access.836820203			Jun 30 07:40:57 PM PDT 24	Jun 30 07:45:36 PM PDT 24	2957855250 ps
T383	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2790158534			Jun 30 08:08:44 PM PDT 24	Jun 30 08:14:58 PM PDT 24	3676842192 ps
T384	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3898371736			Jun 30 08:08:23 PM PDT 24	Jun 30 08:15:56 PM PDT 24	3455020304 ps
T119	/workspace/coverage/default/2.chip_sw_edn_boot_mode.3470422745			Jun 30 07:54:49 PM PDT 24	Jun 30 08:04:46 PM PDT 24	3491314338 ps
T122	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.537026321			Jun 30 07:45:15 PM PDT 24	Jun 30 08:28:52 PM PDT 24	11088078072 ps
T59	/workspace/coverage/default/0.chip_tap_straps_rma.3177911471			Jun 30 07:33:15 PM PDT 24	Jun 30 07:43:07 PM PDT 24	6763550272 ps
T206	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.42552418			Jun 30 07:28:21 PM PDT 24	Jun 30 07:38:06 PM PDT 24	4173768704 ps
T385	/workspace/coverage/default/0.chip_sw_kmac_smoketest.106401434			Jun 30 07:38:34 PM PDT 24	Jun 30 07:43:20 PM PDT 24	2996506840 ps
T169	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3837788354			Jun 30 08:03:44 PM PDT 24	Jun 30 08:18:44 PM PDT 24	5846109724 ps
T154	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3251382615			Jun 30 08:10:48 PM PDT 24	Jun 30 08:16:35 PM PDT 24	3463478384 ps
T71	/workspace/coverage/default/1.chip_tap_straps_testunlock0.3361131359			Jun 30 07:47:59 PM PDT 24	Jun 30 07:53:01 PM PDT 24	3838074325 ps
T85	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2400479505			Jun 30 07:54:21 PM PDT 24	Jun 30 08:26:48 PM PDT 24	13243297360 ps
T244	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3236656349			Jun 30 07:41:26 PM PDT 24	Jun 30 07:46:18 PM PDT 24	3159939864 ps
T144	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.4139935856			Jun 30 08:02:19 PM PDT 24	Jun 30 08:33:04 PM PDT 24	9035563464 ps
T439	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2542623454			Jun 30 07:29:56 PM PDT 24	Jun 30 07:48:38 PM PDT 24	6108743256 ps
T659	/workspace/coverage/default/0.chip_sw_edn_sw_mode.3482463779			Jun 30 07:29:58 PM PDT 24	Jun 30 07:50:18 PM PDT 24	5650679840 ps
T48	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2673802806			Jun 30 07:43:08 PM PDT 24	Jun 30 07:55:32 PM PDT 24	5875612616 ps
T708	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2734766511			Jun 30 08:07:26 PM PDT 24	Jun 30 08:13:59 PM PDT 24	3895768880 ps
T325	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1011888218			Jun 30 07:34:45 PM PDT 24	Jun 30 07:46:42 PM PDT 24	4618170030 ps
T211	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2931996370			Jun 30 07:55:41 PM PDT 24	Jun 30 08:39:35 PM PDT 24	13056140070 ps
T33	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3424240336			Jun 30 07:53:04 PM PDT 24	Jun 30 08:56:12 PM PDT 24	20294335952 ps
T210	/workspace/coverage/default/81.chip_sw_all_escalation_resets.2079227965			Jun 30 08:10:08 PM PDT 24	Jun 30 08:20:24 PM PDT 24	4962447340 ps
T54	/workspace/coverage/default/0.rom_e2e_shutdown_output.2359381408			Jun 30 07:40:24 PM PDT 24	Jun 30 08:56:28 PM PDT 24	23291793395 ps
T883	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1774633913			Jun 30 07:28:41 PM PDT 24	Jun 30 07:36:07 PM PDT 24	4860287228 ps
T706	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1634832964			Jun 30 08:03:00 PM PDT 24	Jun 30 08:09:31 PM PDT 24	3830310810 ps
T57	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2012445217			Jun 30 07:41:08 PM PDT 24	Jun 30 08:47:35 PM PDT 24	16262890706 ps
T884	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2534974435			Jun 30 07:29:18 PM PDT 24	Jun 30 07:33:50 PM PDT 24	2829578044 ps
T1	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.387003795			Jun 30 07:49:59 PM PDT 24	Jun 30 07:55:40 PM PDT 24	4549122604 ps
T65	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1479010751			Jun 30 08:00:26 PM PDT 24	Jun 30 08:12:41 PM PDT 24	8504328750 ps
T34	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2575824713			Jun 30 07:43:50 PM PDT 24	Jun 30 07:51:42 PM PDT 24	4442919327 ps
T102	/workspace/coverage/default/1.chip_sw_aes_idle.1257860681			Jun 30 07:45:45 PM PDT 24	Jun 30 07:49:40 PM PDT 24	2233521000 ps
T103	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1426855432			Jun 30 08:04:30 PM PDT 24	Jun 30 08:17:48 PM PDT 24	5004305480 ps
T31	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.210268750			Jun 30 07:49:13 PM PDT 24	Jun 30 07:55:47 PM PDT 24	6073873420 ps
T58	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1857326614			Jun 30 08:03:58 PM PDT 24	Jun 30 08:57:37 PM PDT 24	14830442376 ps
T104	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.312751298			Jun 30 07:55:45 PM PDT 24	Jun 30 08:06:41 PM PDT 24	7862934878 ps
T105	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3073581841			Jun 30 07:29:04 PM PDT 24	Jun 30 08:38:22 PM PDT 24	18524862407 ps
T106	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2237779102			Jun 30 07:46:00 PM PDT 24	Jun 30 09:03:26 PM PDT 24	15304403320 ps
T195	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1615141264			Jun 30 07:29:05 PM PDT 24	Jun 30 07:40:13 PM PDT 24	5254494893 ps
T724	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2691664524			Jun 30 07:54:49 PM PDT 24	Jun 30 08:02:24 PM PDT 24	3672852360 ps
T327	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1804122333			Jun 30 07:45:11 PM PDT 24	Jun 30 07:48:43 PM PDT 24	2326003265 ps
T72	/workspace/coverage/default/1.chip_jtag_mem_access.106717189			Jun 30 07:39:59 PM PDT 24	Jun 30 08:10:59 PM PDT 24	14027917970 ps
T214	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3382960182			Jun 30 07:45:09 PM PDT 24	Jun 30 08:06:47 PM PDT 24	7203369624 ps
T681	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3109606012			Jun 30 07:58:42 PM PDT 24	Jun 30 08:03:50 PM PDT 24	2933974494 ps
T382	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2603712793			Jun 30 08:05:01 PM PDT 24	Jun 30 08:51:03 PM PDT 24	11890088260 ps
T683	/workspace/coverage/default/0.chip_sw_hmac_multistream.2990428130			Jun 30 07:28:54 PM PDT 24	Jun 30 08:01:24 PM PDT 24	8052144692 ps
T35	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2685472452			Jun 30 07:55:31 PM PDT 24	Jun 30 08:03:38 PM PDT 24	3614099000 ps
T204	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4007571287			Jun 30 07:55:39 PM PDT 24	Jun 30 08:29:50 PM PDT 24	7627476216 ps
T249	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3321174439			Jun 30 08:03:14 PM PDT 24	Jun 30 09:48:45 PM PDT 24	25937204700 ps
T298	/workspace/coverage/default/0.chip_plic_all_irqs_0.338240217			Jun 30 07:32:06 PM PDT 24	Jun 30 07:50:53 PM PDT 24	5497627256 ps
T113	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.194521061			Jun 30 07:47:48 PM PDT 24	Jun 30 07:59:30 PM PDT 24	4768476067 ps
T280	/workspace/coverage/default/0.chip_sw_hmac_enc.3748567113			Jun 30 07:28:19 PM PDT 24	Jun 30 07:33:29 PM PDT 24	2632293012 ps
T171	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3621638779			Jun 30 07:59:53 PM PDT 24	Jun 30 08:03:49 PM PDT 24	3068275593 ps
T250	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2392090399			Jun 30 08:03:49 PM PDT 24	Jun 30 09:05:01 PM PDT 24	13045349976 ps
T120	/workspace/coverage/default/1.chip_sw_edn_auto_mode.2781681440			Jun 30 07:45:08 PM PDT 24	Jun 30 08:03:19 PM PDT 24	4521609980 ps
T281	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.1182217111			Jun 30 07:42:07 PM PDT 24	Jun 30 08:04:06 PM PDT 24	5750652812 ps
T205	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2346610759			Jun 30 07:33:28 PM PDT 24	Jun 30 07:46:31 PM PDT 24	4173596750 ps
T282	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3515938087			Jun 30 08:09:17 PM PDT 24	Jun 30 08:17:24 PM PDT 24	4273810936 ps
T283	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2834284822			Jun 30 07:47:57 PM PDT 24	Jun 30 07:52:31 PM PDT 24	3063689149 ps
T263	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1254927013			Jun 30 07:30:49 PM PDT 24	Jun 30 07:40:13 PM PDT 24	7980517171 ps
T291	/workspace/coverage/default/22.chip_sw_all_escalation_resets.3973534431			Jun 30 08:03:34 PM PDT 24	Jun 30 08:15:29 PM PDT 24	5508837266 ps
T124	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.4085695987			Jun 30 07:57:41 PM PDT 24	Jun 30 08:04:33 PM PDT 24	6377935474 ps
T212	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2683237716			Jun 30 07:56:56 PM PDT 24	Jun 30 08:32:01 PM PDT 24	8240874466 ps
T527	/workspace/coverage/default/66.chip_sw_all_escalation_resets.3140707794			Jun 30 08:08:26 PM PDT 24	Jun 30 08:22:37 PM PDT 24	5672028200 ps
T55	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2363954326			Jun 30 08:05:51 PM PDT 24	Jun 30 09:16:30 PM PDT 24	14821037002 ps
T528	/workspace/coverage/default/0.chip_sw_flash_crash_alert.14759992			Jun 30 07:35:20 PM PDT 24	Jun 30 07:48:23 PM PDT 24	5893059048 ps
T73	/workspace/coverage/default/1.chip_tap_straps_prod.2180781926			Jun 30 07:48:28 PM PDT 24	Jun 30 08:17:17 PM PDT 24	12980312885 ps
T264	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1099969570			Jun 30 07:46:04 PM PDT 24	Jun 30 07:57:43 PM PDT 24	8954690504 ps
T56	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2560507834			Jun 30 07:39:46 PM PDT 24	Jun 30 08:57:38 PM PDT 24	14511686916 ps
T885	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1029123248			Jun 30 07:58:42 PM PDT 24	Jun 30 08:04:14 PM PDT 24	2473041200 ps
T886	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.4050580415			Jun 30 07:40:19 PM PDT 24	Jun 30 08:44:35 PM PDT 24	15432109086 ps
T529	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1860957086			Jun 30 07:47:06 PM PDT 24	Jun 30 08:04:04 PM PDT 24	9331576100 ps
T116	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4107267083			Jun 30 07:29:21 PM PDT 24	Jun 30 08:00:31 PM PDT 24	8864577574 ps
T332	/workspace/coverage/default/6.chip_sw_all_escalation_resets.1869917580			Jun 30 08:00:37 PM PDT 24	Jun 30 08:12:10 PM PDT 24	4436035692 ps
T213	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4187929421			Jun 30 07:55:49 PM PDT 24	Jun 30 08:35:41 PM PDT 24	11134084942 ps
T887	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3801315552			Jun 30 07:54:00 PM PDT 24	Jun 30 08:06:58 PM PDT 24	8307680984 ps
T231	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2217067062			Jun 30 07:53:09 PM PDT 24	Jun 30 08:02:54 PM PDT 24	3592462662 ps
T166	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1404773489			Jun 30 08:00:49 PM PDT 24	Jun 30 08:09:21 PM PDT 24	6973388271 ps
T738	/workspace/coverage/default/71.chip_sw_all_escalation_resets.415018851			Jun 30 08:08:42 PM PDT 24	Jun 30 08:21:26 PM PDT 24	6409573656 ps
T314	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2019751664			Jun 30 07:29:24 PM PDT 24	Jun 30 08:10:26 PM PDT 24	19989562878 ps
T221	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2534437445			Jun 30 07:57:36 PM PDT 24	Jun 30 08:36:55 PM PDT 24	20080963853 ps
T180	/workspace/coverage/default/4.chip_tap_straps_dev.3116111462			Jun 30 07:59:25 PM PDT 24	Jun 30 08:09:41 PM PDT 24	5887838450 ps
T888	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.4285487958			Jun 30 07:29:53 PM PDT 24	Jun 30 07:34:23 PM PDT 24	3081976448 ps
T889	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2236940910			Jun 30 08:03:33 PM PDT 24	Jun 30 08:07:42 PM PDT 24	2853473516 ps
T155	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.971718726			Jun 30 07:41:42 PM PDT 24	Jun 30 07:46:10 PM PDT 24	3034598059 ps
T328	/workspace/coverage/default/0.chip_sw_otbn_randomness.2468412175			Jun 30 07:29:26 PM PDT 24	Jun 30 07:42:34 PM PDT 24	5964982280 ps
T207	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.968491016			Jun 30 08:01:26 PM PDT 24	Jun 30 08:11:17 PM PDT 24	4142115398 ps
T430	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.856872546			Jun 30 07:44:11 PM PDT 24	Jun 30 07:50:39 PM PDT 24	3518864240 ps
T890	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1000257386			Jun 30 07:33:12 PM PDT 24	Jun 30 07:40:30 PM PDT 24	5149387656 ps
T891	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2153603210			Jun 30 07:47:29 PM PDT 24	Jun 30 07:56:02 PM PDT 24	3114201798 ps
T296	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3890638269			Jun 30 08:02:24 PM PDT 24	Jun 30 08:16:36 PM PDT 24	5504974248 ps
T892	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1442619842			Jun 30 08:00:43 PM PDT 24	Jun 30 08:05:59 PM PDT 24	3473516840 ps
T893	/workspace/coverage/default/0.chip_sw_uart_smoketest.2146302170			Jun 30 07:40:33 PM PDT 24	Jun 30 07:44:59 PM PDT 24	2875735270 ps
T145	/workspace/coverage/default/0.chip_sw_power_idle_load.2942203789			Jun 30 07:36:25 PM PDT 24	Jun 30 07:46:43 PM PDT 24	4451880082 ps
T336	/workspace/coverage/default/82.chip_sw_all_escalation_resets.359249300			Jun 30 08:09:50 PM PDT 24	Jun 30 08:23:26 PM PDT 24	6088259620 ps
T894	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3629740727			Jun 30 07:43:05 PM PDT 24	Jun 30 08:49:51 PM PDT 24	14798558186 ps
T719	/workspace/coverage/default/1.chip_sw_all_escalation_resets.203813814			Jun 30 07:41:18 PM PDT 24	Jun 30 07:52:54 PM PDT 24	6042410080 ps
T170	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.871732293			Jun 30 07:56:26 PM PDT 24	Jun 30 08:03:39 PM PDT 24	3704538274 ps
T110	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1984598566			Jun 30 07:43:18 PM PDT 24	Jun 30 08:46:54 PM PDT 24	17968092260 ps
T176	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1538278579			Jun 30 07:30:54 PM PDT 24	Jun 30 09:06:50 PM PDT 24	42860356760 ps
T345	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3139641270			Jun 30 07:57:58 PM PDT 24	Jun 30 08:43:11 PM PDT 24	24895905480 ps
T707	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1740633773			Jun 30 08:02:26 PM PDT 24	Jun 30 08:09:12 PM PDT 24	4134648630 ps
T245	/workspace/coverage/default/0.chip_sw_rv_timer_irq.4285138837			Jun 30 07:28:37 PM PDT 24	Jun 30 07:31:33 PM PDT 24	2965627728 ps
T895	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3899870634			Jun 30 08:02:02 PM PDT 24	Jun 30 08:29:17 PM PDT 24	8369699796 ps
T896	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.252932780			Jun 30 07:43:14 PM PDT 24	Jun 30 07:50:57 PM PDT 24	4385594832 ps
T684	/workspace/coverage/default/43.chip_sw_all_escalation_resets.4053456243			Jun 30 08:05:50 PM PDT 24	Jun 30 08:17:27 PM PDT 24	5943244460 ps
T335	/workspace/coverage/default/70.chip_sw_all_escalation_resets.4263333350			Jun 30 08:08:55 PM PDT 24	Jun 30 08:18:53 PM PDT 24	4605985880 ps
T357	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2497796793			Jun 30 07:40:25 PM PDT 24	Jun 30 08:56:54 PM PDT 24	15431204920 ps
T30	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3570436787			Jun 30 08:01:33 PM PDT 24	Jun 30 08:12:32 PM PDT 24	4246368312 ps
T230	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115619205			Jun 30 08:06:40 PM PDT 24	Jun 30 08:14:28 PM PDT 24	4127088928 ps
T739	/workspace/coverage/default/87.chip_sw_all_escalation_resets.752133159			Jun 30 08:10:15 PM PDT 24	Jun 30 08:23:39 PM PDT 24	6000923410 ps
T897	/workspace/coverage/default/2.chip_sw_aes_enc.839082966			Jun 30 07:53:09 PM PDT 24	Jun 30 07:57:59 PM PDT 24	2673479590 ps
T898	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.909611484			Jun 30 08:02:26 PM PDT 24	Jun 30 08:11:19 PM PDT 24	7585644670 ps
T899	/workspace/coverage/default/2.chip_sw_edn_sw_mode.1986586215			Jun 30 07:55:07 PM PDT 24	Jun 30 08:21:34 PM PDT 24	6454771860 ps
T107	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.641643892			Jun 30 07:44:27 PM PDT 24	Jun 30 07:53:04 PM PDT 24	18169015000 ps
T658	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.793925302			Jun 30 07:55:05 PM PDT 24	Jun 30 09:46:11 PM PDT 24	23711279902 ps
T275	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1978605930			Jun 30 08:01:26 PM PDT 24	Jun 30 08:14:00 PM PDT 24	5922727088 ps
T216	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.42451140			Jun 30 07:30:20 PM PDT 24	Jun 30 08:29:44 PM PDT 24	15839829296 ps
T352	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072711359			Jun 30 08:04:14 PM PDT 24	Jun 30 08:11:31 PM PDT 24	4323876378 ps
T153	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1726188986			Jun 30 07:44:12 PM PDT 24	Jun 30 11:19:46 PM PDT 24	254647415436 ps
T717	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.734581468			Jun 30 08:01:23 PM PDT 24	Jun 30 08:09:29 PM PDT 24	3623448694 ps
T235	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3408241363			Jun 30 07:58:12 PM PDT 24	Jun 30 08:11:42 PM PDT 24	5731194271 ps
T297	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2610783188			Jun 30 07:28:46 PM PDT 24	Jun 30 08:36:40 PM PDT 24	34246354505 ps
T69	/workspace/coverage/default/2.chip_tap_straps_testunlock0.3243299294			Jun 30 07:58:22 PM PDT 24	Jun 30 08:04:46 PM PDT 24	3833665962 ps
T337	/workspace/coverage/default/40.chip_sw_all_escalation_resets.2238035204			Jun 30 08:05:33 PM PDT 24	Jun 30 08:14:56 PM PDT 24	5832110190 ps
T344	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4213961050			Jun 30 07:59:07 PM PDT 24	Jun 30 08:04:37 PM PDT 24	4013539219 ps
T38	/workspace/coverage/default/2.chip_sw_gpio_smoketest.2464306324			Jun 30 07:58:47 PM PDT 24	Jun 30 08:05:20 PM PDT 24	3327489831 ps
T26	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2904822747			Jun 30 07:40:58 PM PDT 24	Jun 30 07:52:14 PM PDT 24	4659885839 ps
T703	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2017348976			Jun 30 08:06:43 PM PDT 24	Jun 30 08:13:31 PM PDT 24	3066326032 ps
T900	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3352195308			Jun 30 07:30:16 PM PDT 24	Jun 30 07:34:39 PM PDT 24	2946900066 ps
T901	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.3791929928			Jun 30 07:45:31 PM PDT 24	Jun 30 07:52:05 PM PDT 24	2874684488 ps
T203	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3930454332			Jun 30 07:44:33 PM PDT 24	Jun 30 08:37:54 PM PDT 24	20204230951 ps
T146	/workspace/coverage/default/1.chip_sw_otbn_smoketest.2146234634			Jun 30 07:51:23 PM PDT 24	Jun 30 08:28:13 PM PDT 24	8322654098 ps
T27	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3118544082			Jun 30 07:40:19 PM PDT 24	Jun 30 07:46:07 PM PDT 24	3267584652 ps
T88	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.705601476			Jun 30 07:52:29 PM PDT 24	Jul 01 12:03:08 AM PDT 24	78392665044 ps
T86	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3817367363			Jun 30 07:28:41 PM PDT 24	Jun 30 07:35:05 PM PDT 24	3652479888 ps
T196	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3670486874			Jun 30 07:44:34 PM PDT 24	Jun 30 07:49:51 PM PDT 24	2736574017 ps
T236	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1619320106			Jun 30 07:43:28 PM PDT 24	Jun 30 08:07:41 PM PDT 24	12260630810 ps
T386	/workspace/coverage/default/56.chip_sw_all_escalation_resets.1781422350			Jun 30 08:07:47 PM PDT 24	Jun 30 08:16:59 PM PDT 24	4673485436 ps
T358	/workspace/coverage/default/0.rom_e2e_asm_init_dev.1442867398			Jun 30 07:42:20 PM PDT 24	Jun 30 08:52:18 PM PDT 24	15017798744 ps
T902	/workspace/coverage/default/1.chip_sw_example_rom.116929169			Jun 30 07:39:56 PM PDT 24	Jun 30 07:42:04 PM PDT 24	2644310022 ps
T702	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2087441151			Jun 30 08:06:28 PM PDT 24	Jun 30 08:15:18 PM PDT 24	3855084006 ps
T2	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1266853118			Jun 30 07:48:36 PM PDT 24	Jun 30 08:19:50 PM PDT 24	21900858704 ps
T396	/workspace/coverage/default/1.chip_sw_power_idle_load.3585522698			Jun 30 07:49:20 PM PDT 24	Jun 30 08:02:09 PM PDT 24	4798191662 ps
T397	/workspace/coverage/default/2.chip_sw_aes_idle.3213175343			Jun 30 07:54:47 PM PDT 24	Jun 30 07:59:41 PM PDT 24	2596838240 ps
T322	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1684801070			Jun 30 07:41:23 PM PDT 24	Jun 30 07:51:14 PM PDT 24	3979438694 ps
T398	/workspace/coverage/default/0.rom_e2e_smoke.1536205240			Jun 30 07:41:04 PM PDT 24	Jun 30 08:48:32 PM PDT 24	15253740800 ps
T399	/workspace/coverage/default/25.chip_sw_all_escalation_resets.1968056266			Jun 30 08:06:07 PM PDT 24	Jun 30 08:15:20 PM PDT 24	5706621132 ps
T400	/workspace/coverage/default/1.rom_e2e_static_critical.3276583699			Jun 30 07:52:24 PM PDT 24	Jun 30 09:14:29 PM PDT 24	17361699046 ps
T401	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.906960428			Jun 30 08:09:22 PM PDT 24	Jun 30 08:17:19 PM PDT 24	3691713728 ps
T121	/workspace/coverage/default/2.chip_sw_edn_auto_mode.1674457804			Jun 30 07:54:36 PM PDT 24	Jun 30 08:06:34 PM PDT 24	3251388984 ps
T402	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.341417336			Jun 30 08:04:40 PM PDT 24	Jun 30 08:12:56 PM PDT 24	4339123180 ps
T903	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.850398398			Jun 30 07:34:05 PM PDT 24	Jun 30 07:53:18 PM PDT 24	8288767431 ps
T904	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3395895283			Jun 30 07:57:07 PM PDT 24	Jun 30 08:06:56 PM PDT 24	4325752220 ps
T162	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1358571108			Jun 30 07:52:06 PM PDT 24	Jun 30 08:18:40 PM PDT 24	8297185044 ps
T905	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1098655295			Jun 30 07:58:09 PM PDT 24	Jun 30 08:05:20 PM PDT 24	3440105632 ps
T353	/workspace/coverage/default/17.chip_sw_all_escalation_resets.3041659165			Jun 30 08:07:10 PM PDT 24	Jun 30 08:19:36 PM PDT 24	4455394382 ps
T800	/workspace/coverage/default/57.chip_sw_all_escalation_resets.2958343640			Jun 30 08:09:18 PM PDT 24	Jun 30 08:24:10 PM PDT 24	6248379558 ps
T315	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.591414713			Jun 30 07:49:32 PM PDT 24	Jun 30 07:52:57 PM PDT 24	2534003808 ps
T906	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1745951317			Jun 30 07:52:42 PM PDT 24	Jun 30 08:03:01 PM PDT 24	5730468804 ps
T299	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3731917985			Jun 30 08:00:59 PM PDT 24	Jun 30 08:10:56 PM PDT 24	4095377256 ps
T907	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.428366186			Jun 30 07:58:05 PM PDT 24	Jun 30 08:02:37 PM PDT 24	2643205582 ps
T908	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1193664726			Jun 30 07:28:11 PM PDT 24	Jun 30 07:40:25 PM PDT 24	5113473048 ps
T161	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1208845619			Jun 30 07:52:29 PM PDT 24	Jun 30 08:36:27 PM PDT 24	32233276074 ps
T801	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.665742241			Jun 30 08:04:56 PM PDT 24	Jun 30 08:11:03 PM PDT 24	3829326176 ps
T798	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1044086949			Jun 30 08:10:03 PM PDT 24	Jun 30 08:17:24 PM PDT 24	4290979060 ps
T909	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1508791566			Jun 30 07:53:43 PM PDT 24	Jun 30 08:04:22 PM PDT 24	5677428288 ps
T331	/workspace/coverage/default/28.chip_sw_all_escalation_resets.332608610			Jun 30 08:04:29 PM PDT 24	Jun 30 08:17:30 PM PDT 24	5400662400 ps
T306	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2705647716			Jun 30 07:55:10 PM PDT 24	Jun 30 08:19:00 PM PDT 24	6911374328 ps
T7	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1378424562			Jun 30 07:33:28 PM PDT 24	Jun 30 07:40:26 PM PDT 24	4640112280 ps
T117	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.458922425			Jun 30 07:32:03 PM PDT 24	Jun 30 07:42:40 PM PDT 24	4392597932 ps
T241	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2088311739			Jun 30 07:32:20 PM PDT 24	Jun 30 07:36:25 PM PDT 24	2422650504 ps
T416	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3413650997			Jun 30 08:06:35 PM PDT 24	Jun 30 08:13:50 PM PDT 24	2949208346 ps
T417	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2806870578			Jun 30 07:49:18 PM PDT 24	Jun 30 07:52:41 PM PDT 24	2899244392 ps
T418	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3031811441			Jun 30 07:28:32 PM PDT 24	Jun 30 07:42:32 PM PDT 24	9772698840 ps
T89	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.794708653			Jun 30 07:33:04 PM PDT 24	Jun 30 10:54:06 PM PDT 24	65282938374 ps
T80	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1832124343			Jun 30 07:58:10 PM PDT 24	Jun 30 08:07:02 PM PDT 24	5305056410 ps
T125	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2135975432			Jun 30 07:33:29 PM PDT 24	Jun 30 07:40:12 PM PDT 24	5987502862 ps
T307	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2835363336			Jun 30 07:46:17 PM PDT 24	Jun 30 08:25:18 PM PDT 24	8007123944 ps
T910	/workspace/coverage/default/0.chip_sw_otbn_smoketest.4196923460			Jun 30 07:40:03 PM PDT 24	Jun 30 08:14:13 PM PDT 24	9656879656 ps
T32	/workspace/coverage/default/0.chip_sw_usbdev_stream.1482429456			Jun 30 07:29:25 PM PDT 24	Jun 30 08:52:10 PM PDT 24	19365862842 ps
T232	/workspace/coverage/default/24.chip_sw_all_escalation_resets.207988989			Jun 30 08:03:39 PM PDT 24	Jun 30 08:14:45 PM PDT 24	4331442308 ps
T114	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2964988277			Jun 30 07:57:16 PM PDT 24	Jun 30 08:07:06 PM PDT 24	3789288407 ps
T118	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3207863185			Jun 30 07:47:25 PM PDT 24	Jun 30 07:59:02 PM PDT 24	4330959920 ps
T255	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1553284912			Jun 30 07:29:04 PM PDT 24	Jun 30 07:53:35 PM PDT 24	6499846448 ps
T256	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2565089081			Jun 30 07:53:19 PM PDT 24	Jun 30 08:01:05 PM PDT 24	7754353680 ps
T257	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2055858690			Jun 30 07:44:49 PM PDT 24	Jun 30 07:48:21 PM PDT 24	2785666082 ps
T258	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3213729369			Jun 30 07:35:27 PM PDT 24	Jun 30 07:39:43 PM PDT 24	2987299374 ps
T259	/workspace/coverage/default/1.chip_sw_kmac_idle.1409689343			Jun 30 07:45:59 PM PDT 24	Jun 30 07:48:56 PM PDT 24	2302363340 ps
T260	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.788573362			Jun 30 07:41:57 PM PDT 24	Jun 30 07:43:43 PM PDT 24	2432924339 ps
T261	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3124433846			Jun 30 07:51:28 PM PDT 24	Jun 30 08:21:42 PM PDT 24	8965200996 ps
T365	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.132604121			Jun 30 07:31:57 PM PDT 24	Jun 30 07:35:56 PM PDT 24	2733006284 ps
T51	/workspace/coverage/default/0.chip_sw_spi_device_tpm.837283218			Jun 30 07:28:41 PM PDT 24	Jun 30 07:35:08 PM PDT 24	3939113378 ps
T326	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2236441802			Jun 30 07:51:42 PM PDT 24	Jun 30 08:02:56 PM PDT 24	3798610566 ps
T276	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1025395298			Jun 30 07:46:29 PM PDT 24	Jun 30 07:56:39 PM PDT 24	4375295948 ps
T718	/workspace/coverage/default/95.chip_sw_all_escalation_resets.2322553195			Jun 30 08:11:19 PM PDT 24	Jun 30 08:19:49 PM PDT 24	4502598530 ps
T911	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.41652149			Jun 30 07:41:10 PM PDT 24	Jun 30 08:29:19 PM PDT 24	11571732904 ps
T731	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3316464078			Jun 30 08:04:08 PM PDT 24	Jun 30 08:11:30 PM PDT 24	4378531976 ps
T217	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3745576983			Jun 30 07:56:03 PM PDT 24	Jun 30 09:06:23 PM PDT 24	18703434104 ps
T912	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1851852235			Jun 30 07:46:35 PM PDT 24	Jun 30 07:52:31 PM PDT 24	2721137532 ps
T913	/workspace/coverage/default/2.rom_e2e_asm_init_rma.2150019623			Jun 30 08:05:17 PM PDT 24	Jun 30 09:09:25 PM PDT 24	14566275185 ps
T914	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.1454287606			Jun 30 07:50:13 PM PDT 24	Jun 30 08:07:23 PM PDT 24	5419998248 ps
T424	/workspace/coverage/default/59.chip_sw_all_escalation_resets.3464917451			Jun 30 08:07:21 PM PDT 24	Jun 30 08:21:40 PM PDT 24	6223527186 ps
T428	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2155543198			Jun 30 08:09:59 PM PDT 24	Jun 30 08:15:53 PM PDT 24	3376792712 ps
T341	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.151178718			Jun 30 07:52:30 PM PDT 24	Jun 30 08:39:08 PM PDT 24	27781925556 ps
T329	/workspace/coverage/default/2.chip_sw_pattgen_ios.1013156678			Jun 30 07:51:06 PM PDT 24	Jun 30 07:55:11 PM PDT 24	2954609228 ps
T172	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1241966651			Jun 30 07:49:07 PM PDT 24	Jun 30 07:55:54 PM PDT 24	3258348624 ps
T368	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119592798			Jun 30 08:08:25 PM PDT 24	Jun 30 08:16:08 PM PDT 24	4588282860 ps
T369	/workspace/coverage/default/1.rom_keymgr_functest.2497410771			Jun 30 07:50:12 PM PDT 24	Jun 30 08:02:24 PM PDT 24	5798075620 ps
T370	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.603965837			Jun 30 08:01:40 PM PDT 24	Jun 30 09:51:07 PM PDT 24	29466969050 ps
T371	/workspace/coverage/default/54.chip_sw_all_escalation_resets.2113519325			Jun 30 08:07:53 PM PDT 24	Jun 30 08:17:53 PM PDT 24	4733533700 ps
T372	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3633165315			Jun 30 08:07:48 PM PDT 24	Jun 30 08:14:39 PM PDT 24	3666814158 ps
T39	/workspace/coverage/default/2.chip_sw_gpio.572058749			Jun 30 07:51:07 PM PDT 24	Jun 30 07:59:14 PM PDT 24	4064587215 ps
T373	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2952838774			Jun 30 08:09:34 PM PDT 24	Jun 30 08:15:14 PM PDT 24	3494731752 ps
T374	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3715946790			Jun 30 07:44:13 PM PDT 24	Jun 30 07:56:46 PM PDT 24	5650167168 ps
T375	/workspace/coverage/default/1.chip_tap_straps_dev.3099355982			Jun 30 07:46:46 PM PDT 24	Jun 30 07:50:06 PM PDT 24	2211466932 ps
T710	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3420762568			Jun 30 07:49:24 PM PDT 24	Jun 30 08:00:47 PM PDT 24	5114913412 ps
T915	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1155639876			Jun 30 07:48:19 PM PDT 24	Jun 30 08:07:45 PM PDT 24	5722562832 ps
T916	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.509690084			Jun 30 07:35:24 PM PDT 24	Jun 30 07:40:31 PM PDT 24	3719690979 ps
T704	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2215924474			Jun 30 08:04:25 PM PDT 24	Jun 30 08:11:26 PM PDT 24	4106324528 ps
T733	/workspace/coverage/default/31.chip_sw_all_escalation_resets.3609245902			Jun 30 08:04:20 PM PDT 24	Jun 30 08:14:31 PM PDT 24	5309650244 ps
T917	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1085614763			Jun 30 07:42:45 PM PDT 24	Jun 30 08:06:27 PM PDT 24	8881506184 ps
T165	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1320200865			Jun 30 07:53:10 PM PDT 24	Jun 30 09:24:09 PM PDT 24	47215071650 ps
T209	/workspace/coverage/default/1.chip_sw_uart_tx_rx.2472592417			Jun 30 07:41:07 PM PDT 24	Jun 30 07:51:40 PM PDT 24	3938860920 ps
T765	/workspace/coverage/default/5.chip_sw_all_escalation_resets.2206043000			Jun 30 08:01:36 PM PDT 24	Jun 30 08:16:19 PM PDT 24	6136556388 ps