Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	512	1			T434	2		T600	4		T667	1
all_values[1]	517	1			T239	1		T434	3		T422	1
all_values[2]	464	1			T434	1		T600	4		T441	1
all_values[3]	464	1			T436	1		T600	3		T662	1
all_values[4]	489	1			T436	2		T662	1		T802	1
all_values[5]	506	1			T480	2		T394	1		T600	4
all_values[6]	462	1			T434	1		T436	1		T821	1
all_values[7]	472	1			T434	1		T539	1		T422	1
all_values[8]	463	1			T434	1		T539	1		T422	1
all_values[9]	449	1			T434	1		T422	1		T436	2
all_values[10]	481	1			T434	2		T436	1		T831	1
all_values[11]	481	1			T239	1		T434	3		T539	1
all_values[12]	456	1			T434	2		T422	1		T394	2
all_values[13]	499	1			T434	3		T435	1		T480	1
all_values[14]	479	1			T434	1		T422	1		T436	1
all_values[15]	472	1			T434	3		T539	2		T435	1
all_values[16]	510	1			T239	1		T434	2		T436	1
all_values[17]	476	1			T434	1		T539	1		T394	1
all_values[18]	467	1			T434	1		T422	2		T480	1
all_values[19]	500	1			T434	2		T811	1		T394	1
all_values[20]	500	1			T434	1		T422	2		T480	1
all_values[21]	479	1			T434	1		T544	1		T600	3
all_values[22]	467	1			T436	2		T544	1		T600	6
all_values[23]	477	1			T539	1		T422	1		T480	2
all_values[24]	446	1			T539	1		T811	1		T852	2
all_values[25]	429	1			T544	1		T600	1		T662	1
all_values[26]	475	1			T79	1		T434	1		T436	1
all_values[27]	468	1			T434	1		T422	1		T600	2
all_values[28]	500	1			T239	1		T434	1		T422	1
all_values[29]	499	1			T79	1		T434	1		T436	1
all_values[30]	485	1			T434	1		T422	1		T394	1
all_values[31]	450	1			T79	1		T434	2		T600	2
all_values[32]	506	1			T79	1		T394	1		T600	3
all_values[33]	472	1			T436	1		T811	1		T600	2
all_values[34]	521	1			T239	1		T434	2		T422	1
all_values[35]	521	1			T79	1		T436	1		T480	1
all_values[36]	449	1			T435	1		T422	1		T480	1
all_values[37]	478	1			T434	1		T422	1		T436	1
all_values[38]	476	1			T79	1		T434	2		T422	1
all_values[39]	491	1			T79	1		T436	2		T821	1
all_values[40]	467	1			T434	2		T480	1		T811	2
all_values[41]	456	1			T434	3		T600	2		T662	1
all_values[42]	489	1			T434	1		T422	1		T436	1
all_values[43]	493	1			T239	1		T436	2		T449	1
all_values[44]	536	1			T434	1		T600	2		T667	1
all_values[45]	503	1			T480	1		T811	1		T611	1
all_values[46]	465	1			T539	1		T811	1		T394	1
all_values[47]	483	1			T434	1		T435	1		T480	1
all_values[48]	506	1			T79	1		T434	1		T539	1
all_values[49]	467	1			T434	1		T539	1		T449	1