Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3741	1			T79	1		T239	4		T434	10
all_values[1]	3735	1			T79	4		T239	1		T434	13
all_values[2]	3755	1			T239	4		T434	9		T435	3
all_values[3]	3737	1			T79	1		T434	9		T435	2
all_values[4]	3723	1			T239	6		T434	4		T422	1
all_values[5]	3707	1			T79	1		T239	5		T434	16
all_values[6]	3765	1			T239	1		T434	5		T435	2
all_values[7]	3801	1			T239	2		T434	7		T435	4
all_values[8]	3670	1			T239	8		T434	12		T422	4
all_values[9]	3819	1			T79	1		T239	4		T434	4
all_values[10]	3762	1			T79	1		T239	2		T434	6
all_values[11]	3794	1			T79	1		T239	4		T434	11
all_values[12]	3802	1			T79	2		T239	1		T434	12
all_values[13]	3788	1			T239	6		T434	9		T435	1
all_values[14]	3746	1			T239	2		T434	6		T435	1
all_values[15]	3740	1			T79	2		T434	8		T422	3
all_values[16]	3703	1			T79	1		T239	3		T434	10
all_values[17]	3754	1			T79	1		T239	3		T434	6
all_values[18]	3763	1			T79	1		T239	3		T434	10
all_values[19]	3956	1			T239	2		T434	7		T422	3
all_values[20]	3788	1			T239	5		T434	7		T422	5
all_values[21]	3772	1			T79	1		T239	3		T434	9
all_values[22]	3674	1			T79	1		T239	4		T434	8
all_values[23]	3795	1			T239	4		T434	8		T435	3
all_values[24]	3737	1			T79	1		T239	3		T434	13
all_values[25]	3674	1			T79	1		T239	6		T434	10
all_values[26]	3723	1			T239	1		T434	10		T435	1
all_values[27]	3655	1			T79	2		T239	4		T434	11
all_values[28]	3714	1			T79	1		T239	1		T434	9
all_values[29]	3792	1			T79	3		T239	4		T434	9
all_values[30]	3819	1			T239	1		T434	7		T422	3
all_values[31]	3682	1			T79	4		T239	3		T434	7
all_values[32]	3649	1			T239	1		T434	6		T435	1
all_values[33]	3752	1			T239	6		T434	4		T435	2
all_values[34]	3705	1			T239	3		T434	6		T422	6
all_values[35]	3721	1			T79	1		T239	3		T434	6
all_values[36]	3700	1			T239	1		T434	6		T435	2
all_values[37]	3774	1			T79	1		T239	2		T434	7
all_values[38]	3719	1			T239	3		T434	9		T435	1
all_values[39]	3774	1			T239	5		T434	7		T435	2
all_values[40]	3641	1			T79	1		T239	2		T434	2
all_values[41]	3942	1			T239	2		T434	11		T422	3
all_values[42]	3687	1			T79	1		T239	6		T434	8
all_values[43]	3793	1			T79	1		T239	4		T434	10
all_values[44]	3923	1			T79	1		T239	2		T434	15
all_values[45]	3757	1			T79	1		T239	3		T434	10
all_values[46]	3690	1			T79	1		T239	3		T434	5
all_values[47]	3851	1			T79	1		T239	6		T434	5
all_values[48]	3727	1			T239	1		T434	6		T435	1
all_values[49]	3787	1			T79	1		T239	1		T434	4
all_values[50]	3736	1			T79	1		T239	3		T434	12
all_values[51]	3695	1			T239	5		T434	7		T435	1
all_values[52]	3683	1			T239	4		T434	4		T422	2
all_values[53]	3864	1			T239	4		T434	8		T435	1
all_values[54]	3686	1			T239	2		T434	12		T422	2
all_values[55]	3724	1			T239	3		T434	10		T422	5
all_values[56]	3831	1			T79	1		T239	6		T434	15
all_values[57]	3744	1			T79	1		T239	5		T434	10
all_values[58]	3807	1			T79	1		T239	3		T434	11
all_values[59]	3787	1			T79	1		T239	4		T434	10
all_values[60]	3868	1			T79	1		T239	5		T434	9
all_values[61]	3745	1			T239	4		T434	6		T435	3
all_values[62]	3767	1			T239	2		T434	8		T435	1
all_values[63]	3826	1			T434	8		T435	2		T422	5