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 LINE       36661
 EXPRESSION (addr_hit[557] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T17
1	0	1	Covered	T4,T5,T17
1	1	0	Covered	T422,T381,T575
1	1	1	Covered	T131,T347,T422

 LINE       36663
 EXPRESSION (addr_hit[558] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T17
1	0	1	Covered	T4,T5,T17
1	1	0	Covered	T530,T541,T460
1	1	1	Covered	T131,T347,T423

 LINE       36665
 EXPRESSION (addr_hit[559] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T17
1	0	1	Covered	T4,T5,T17
1	1	0	Covered	T480,T381,T542
1	1	1	Covered	T1,T12,T13

 LINE       36668
 EXPRESSION (addr_hit[560] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T17
1	0	1	Covered	T4,T5,T17
1	1	0	Covered	T541,T381,T558
1	1	1	Covered	T131,T347,T393

 LINE       36671
 EXPRESSION (addr_hit[561] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T17
1	0	1	Covered	T4,T5,T17
1	1	0	Covered	T541,T381,T421
1	1	1	Covered	T77,T131,T239

 LINE       36674
 EXPRESSION (addr_hit[562] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T17
1	0	1	Covered	T4,T5,T17
1	1	0	Covered	T530,T381,T542
1	1	1	Covered	T131,T347,T520

 LINE       36677
 EXPRESSION (addr_hit[563] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T17
1	0	1	Covered	T4,T5,T17
1	1	0	Covered	T530,T541,T381
1	1	1	Covered	T131,T347,T521

 LINE       36680
 EXPRESSION (addr_hit[564] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T17
1	0	1	Covered	T4,T5,T17
1	1	0	Covered	T530,T541,T393
1	1	1	Covered	T2,T14,T15

 LINE       36683
 EXPRESSION (addr_hit[565] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T17
1	0	1	Covered	T4,T5,T17
1	1	0	Covered	T541,T393,T444
1	1	1	Covered	T3,T131,T347

 LINE       36686
 EXPRESSION (addr_hit[566] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T17
1	0	1	Covered	T4,T5,T17
1	1	0	Covered	T541,T381,T560
1	1	1	Covered	T11,T131,T523

 LINE       36689
 EXPRESSION (addr_hit[567] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T17
1	0	1	Covered	T4,T5,T17
1	1	0	Covered	T381,T556,T546
1	1	1	Covered	T1,T2,T14

 LINE       40162
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3