Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	131670	1			T79	84		T80	5		T82	16
values[2]	7443	1			T247	1		T450	1		T532	3
values[3]	2691	1			T554	5		T612	1		T867	2
values[4]	1610	1			T554	2		T647	7		T847	58
values[5]	1193	1			T554	1		T647	9		T847	37
values[6]	744	1			T554	1		T647	1		T847	17
values[7]	553	1			T554	3		T847	7		T496	9
values[8]	469	1			T554	1		T847	6		T496	7
values[9]	435	1			T554	1		T847	20		T496	5
values[10]	428	1			T554	3		T847	27		T496	5
values[11]	338	1			T554	1		T847	9		T496	1
values[12]	338	1			T554	4		T847	3		T496	3
values[13]	346	1			T554	6		T496	4		T470	2
values[14]	346	1			T554	1		T496	3		T470	2
values[15]	353	1			T554	1		T496	10		T470	2
values[16]	360	1			T554	1		T496	15		T470	2
values[17]	292	1			T554	4		T496	1		T470	2
values[18]	292	1			T554	2		T496	1		T470	2
values[19]	344	1			T554	3		T496	3		T470	2
values[20]	320	1			T554	2		T496	2		T470	2
values[21]	308	1			T554	1		T496	4		T470	2
values[22]	369	1			T554	2		T496	3		T470	2
values[23]	299	1			T554	7		T496	5		T470	2
values[24]	326	1			T554	2		T496	2		T470	2
values[25]	295	1			T554	2		T496	3		T470	2
values[26]	307	1			T554	1		T496	1		T470	2
values[27]	269	1			T554	2		T496	2		T470	2
values[28]	300	1			T554	2		T496	1		T470	2
values[29]	326	1			T554	2		T496	5		T470	2
values[30]	351	1			T554	4		T496	3		T470	2
values[31]	272	1			T554	2		T496	3		T470	2
values[32]	296	1			T554	1		T496	3		T470	2
values[33]	281	1			T554	3		T496	2		T470	2
values[34]	292	1			T554	3		T496	2		T470	2
values[35]	284	1			T554	3		T496	3		T470	2
values[36]	304	1			T554	2		T496	4		T470	2
values[37]	304	1			T554	5		T496	2		T470	2
values[38]	346	1			T554	2		T496	5		T470	2
values[39]	281	1			T554	2		T496	4		T470	2
values[40]	322	1			T554	1		T496	2		T470	2
values[41]	288	1			T554	2		T496	6		T470	2
values[42]	292	1			T554	3		T496	4		T470	2
values[43]	327	1			T554	3		T496	3		T470	2
values[44]	356	1			T554	1		T496	2		T470	2
values[45]	259	1			T554	4		T496	4		T470	2
values[46]	274	1			T554	4		T496	3		T470	2
values[47]	281	1			T554	7		T496	2		T470	2
values[48]	300	1			T554	11		T496	3		T470	2
values[49]	263	1			T554	2		T496	3		T470	2
values[50]	286	1			T554	1		T496	1		T470	2
values[51]	298	1			T554	3		T496	4		T470	2
values[52]	275	1			T554	3		T496	2		T470	2
values[53]	242	1			T554	3		T496	3		T470	2
values[54]	290	1			T554	1		T496	7		T470	2
values[55]	277	1			T554	4		T496	6		T470	2
values[56]	302	1			T554	1		T496	1		T470	2
values[57]	260	1			T554	1		T496	2		T470	2
values[58]	221	1			T554	1		T496	5		T470	2
values[59]	241	1			T554	6		T496	2		T470	2
values[60]	254	1			T554	5		T496	2		T470	2
values[61]	260	1			T554	3		T496	4		T470	2
values[62]	243	1			T554	2		T496	4		T470	2
values[63]	257	1			T554	11		T496	2		T470	2
values[64]	253	1			T554	5		T496	2		T470	2
values[65]	254	1			T554	4		T496	1		T470	2
values[66]	174	1			T554	2		T496	1		T470	2
values[67]	156	1			T554	1		T496	2		T470	2
values[68]	150	1			T554	3		T496	1		T470	2
values[69]	155	1			T554	1		T496	1		T470	2
values[70]	133	1			T554	2		T496	1		T470	2
values[71]	149	1			T554	2		T496	2		T470	2
values[72]	159	1			T554	1		T496	2		T470	2
values[73]	140	1			T554	2		T496	1		T470	2
values[74]	120	1			T554	2		T496	1		T470	2
values[75]	155	1			T554	3		T496	2		T470	2
values[76]	137	1			T554	8		T496	3		T470	2
values[77]	119	1			T554	4		T496	5		T470	2
values[78]	106	1			T554	1		T496	7		T470	2
values[79]	88	1			T554	1		T496	4		T470	2
values[80]	95	1			T554	1		T496	3		T470	2
values[81]	113	1			T554	4		T496	1		T470	2
values[82]	132	1			T554	5		T496	2		T470	2
values[83]	93	1			T554	4		T496	1		T470	2
values[84]	116	1			T554	2		T496	2		T470	2
values[85]	87	1			T554	3		T496	2		T470	2
values[86]	100	1			T554	3		T496	2		T470	2
values[87]	112	1			T554	1		T496	2		T470	2
values[88]	81	1			T554	6		T496	3		T470	2
values[89]	89	1			T554	3		T496	1		T470	2
values[90]	100	1			T554	1		T496	2		T470	2
values[91]	93	1			T554	2		T496	3		T470	2
values[92]	109	1			T554	1		T496	5		T470	2
values[93]	121	1			T554	1		T496	13		T470	2
values[94]	161	1			T554	3		T496	11		T470	5
values[95]	122	1			T554	2		T496	7		T470	4
values[96]	109	1			T554	1		T496	4		T470	4
values[97]	89	1			T554	1		T496	2		T470	5
values[98]	103	1			T554	1		T496	3		T470	3
values[99]	103	1			T554	7		T496	2		T470	2
values[100]	108	1			T554	4		T496	1		T470	2
values[101]	121	1			T554	3		T496	2		T470	3
values[102]	134	1			T554	6		T496	2		T470	2
values[103]	107	1			T554	9		T496	6		T470	2
values[104]	120	1			T554	9		T496	5		T470	3
values[105]	114	1			T554	3		T496	3		T470	2
values[106]	113	1			T554	2		T496	1		T470	2
values[107]	122	1			T554	6		T496	3		T470	5
values[108]	123	1			T554	4		T496	4		T470	3
values[109]	100	1			T554	2		T496	3		T470	4
values[110]	87	1			T554	1		T496	6		T470	3
values[111]	114	1			T554	1		T496	3		T470	5
values[112]	87	1			T554	5		T496	4		T470	2
values[113]	94	1			T554	5		T496	2		T470	4
values[114]	107	1			T554	8		T496	4		T470	6
values[115]	113	1			T554	2		T496	5		T470	3
values[116]	102	1			T554	1		T496	9		T470	7
values[117]	104	1			T496	3		T470	5		T481	2
values[118]	103	1			T496	1		T470	3		T481	1
values[119]	83	1			T496	1		T470	5		T481	4
values[120]	86	1			T496	2		T470	6		T481	1
values[121]	99	1			T496	1		T470	4		T481	4
values[122]	94	1			T496	2		T470	2		T481	3
values[123]	74	1			T496	3		T470	3		T481	1
values[124]	98	1			T496	4		T470	2		T481	1
values[125]	132	1			T496	1		T470	3		T481	3
values[126]	186	1			T496	7		T470	3		T481	1
values[127]	1049	1			T496	19		T470	57		T481	29
values[128]	7497	1			T496	13		T470	622		T481	300