Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.10	95.45	93.86	95.43		94.82	97.53	99.55

Total tests in report: 2900

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.96	40.96	45.98	45.98	44.96	44.96	35.21	35.21			59.39	59.39	59.44	59.44	0.80	0.80	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3016758104
50.47	9.51	51.89	5.91	60.82	15.86	35.71	0.50			69.91	10.52	82.52	23.08	1.97	1.17	/workspace/coverage/cover_reg_top/13.chip_csr_rw.80648164
56.44	5.96	63.87	11.98	62.63	1.81	43.47	7.76			70.43	0.51	82.52	0.00	15.70	13.72	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.78640338
61.42	4.99	75.21	11.34	69.97	7.34	44.61	1.14			80.54	10.12	82.52	0.00	15.70	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.821281210
65.34	3.92	75.21	0.00	70.26	0.29	44.61	0.00			80.54	0.00	82.52	0.00	38.93	23.23	/workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.937712506
68.84	3.49	81.28	6.06	74.66	4.40	48.51	3.90			82.57	2.03	87.06	4.55	38.93	0.00	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1245433899
71.29	2.46	81.28	0.00	74.66	0.00	48.51	0.00			82.57	0.00	87.06	0.00	53.67	14.75	/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1321997172
73.71	2.41	81.28	0.00	74.66	0.00	63.00	14.48			82.57	0.00	87.06	0.00	53.67	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3198597143
75.69	1.98	81.28	0.00	74.66	0.00	63.00	0.00			82.57	0.00	87.06	0.00	65.55	11.88	/workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3301574073
77.53	1.84	82.94	1.66	76.00	1.34	65.75	2.75			83.98	1.40	90.91	3.85	65.60	0.05	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2839271323
79.14	1.61	85.39	2.46	79.29	3.28	66.63	0.88			86.87	2.90	91.08	0.17	65.60	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3512912499
80.54	1.39	86.38	0.99	79.74	0.46	73.11	6.49			87.12	0.25	91.26	0.17	65.61	0.01	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3416710041
81.89	1.35	86.38	0.00	80.17	0.43	73.11	0.00			87.22	0.10	91.26	0.00	73.21	7.60	/workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3924119100
83.06	1.16	88.48	2.10	82.18	2.01	73.64	0.53			89.56	2.34	91.26	0.00	73.21	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.803130096
84.19	1.14	88.52	0.03	82.18	0.00	80.43	6.79			89.56	0.00	91.26	0.00	73.21	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1679090876
85.27	1.08	88.53	0.01	82.54	0.36	81.18	0.75			89.61	0.05	91.26	0.00	78.52	5.31	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2015494496
86.16	0.89	88.53	0.00	82.54	0.00	81.18	0.00			89.61	0.00	91.26	0.00	83.84	5.32	/workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.4024167385
87.00	0.85	89.27	0.74	82.76	0.22	81.19	0.01			89.86	0.25	95.10	3.85	83.84	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1467847625
87.69	0.69	89.27	0.00	82.79	0.03	81.19	0.00			89.86	0.00	95.10	0.00	87.95	4.10	/workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1735777230
88.36	0.67	89.28	0.02	82.83	0.04	83.57	2.38			89.86	0.00	95.10	0.00	89.51	1.56	/workspace/coverage/default/1.chip_sw_alert_test.3383454398
88.97	0.61	90.40	1.12	83.92	1.09	84.00	0.43			90.86	1.01	95.10	0.00	89.51	0.00	/workspace/coverage/default/2.chip_sw_gpio_smoketest.217575456
89.44	0.47	90.58	0.18	84.25	0.32	85.82	1.82			91.20	0.34	95.28	0.17	89.51	0.00	/workspace/coverage/default/1.chip_jtag_mem_access.201308257
89.86	0.42	90.59	0.01	86.33	2.08	85.82	0.00			91.20	0.00	95.28	0.00	89.93	0.42	/workspace/coverage/cover_reg_top/8.chip_tl_errors.2657315597
90.27	0.42	91.50	0.91	86.60	0.27	86.31	0.49			91.33	0.13	95.98	0.70	89.93	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1739160699
90.65	0.38	91.90	0.40	87.43	0.84	86.49	0.18			92.19	0.86	95.98	0.00	89.93	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.2138198902
91.01	0.35	91.91	0.01	87.44	0.01	88.58	2.09			92.19	0.00	95.98	0.00	89.93	0.00	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3451692205
91.34	0.34	92.61	0.70	88.04	0.60	88.70	0.11			92.61	0.41	96.15	0.17	89.94	0.01	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2515482068
91.66	0.32	92.61	0.00	88.04	0.00	88.70	0.00			92.61	0.00	96.15	0.00	91.86	1.92	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.256035780
91.97	0.31	92.61	0.00	88.04	0.00	88.70	0.00			92.61	0.00	96.15	0.00	93.70	1.84	/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.25615360
92.27	0.30	93.10	0.49	88.46	0.42	89.14	0.44			93.05	0.44	96.15	0.00	93.70	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.695657672
92.53	0.27	93.10	0.00	88.59	0.13	89.14	0.00			93.05	0.00	96.15	0.00	95.17	1.47	/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.543210333
92.73	0.20	93.10	0.00	88.68	0.09	89.14	0.00			93.05	0.00	96.15	0.00	96.29	1.12	/workspace/coverage/cover_reg_top/70.xbar_access_same_device.552789125
92.93	0.19	93.38	0.28	88.92	0.24	89.48	0.34			93.35	0.30	96.15	0.00	96.29	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2457028822
93.10	0.18	93.61	0.23	89.54	0.62	89.51	0.03			93.53	0.19	96.15	0.00	96.29	0.00	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.4147488119
93.27	0.17	93.79	0.18	89.67	0.13	89.72	0.21			93.66	0.13	96.50	0.35	96.29	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1426944830
93.43	0.16	93.79	0.00	89.67	0.00	90.68	0.95			93.66	0.00	96.50	0.00	96.29	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.154129962
93.58	0.15	93.79	0.00	89.86	0.19	90.68	0.00			93.71	0.05	96.50	0.00	96.96	0.67	/workspace/coverage/cover_reg_top/48.xbar_stress_all.3767393878
93.72	0.14	94.07	0.28	90.12	0.26	90.96	0.28			93.71	0.00	96.50	0.00	96.96	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.968897475
93.84	0.12	94.07	0.00	90.12	0.00	91.70	0.74			93.71	0.00	96.50	0.00	96.96	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3136918863
93.96	0.11	94.07	0.00	90.12	0.00	92.36	0.65			93.71	0.00	96.50	0.00	96.99	0.04	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.4090180772
94.07	0.11	94.07	0.00	90.79	0.67	92.36	0.00			93.71	0.00	96.50	0.00	96.99	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.386249097
94.18	0.11	94.07	0.00	91.10	0.31	92.36	0.00			94.07	0.36	96.50	0.00	96.99	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2265117963
94.28	0.10	94.12	0.05	91.10	0.01	92.90	0.54			94.08	0.01	96.50	0.00	96.99	0.00	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3344520813
94.38	0.10	94.12	0.00	91.15	0.04	92.90	0.00			94.08	0.00	96.50	0.00	97.52	0.53	/workspace/coverage/cover_reg_top/47.xbar_access_same_device.3881929084
94.46	0.09	94.15	0.03	91.26	0.11	93.05	0.15			94.13	0.06	96.68	0.17	97.52	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2465120182
94.54	0.08	94.15	0.00	91.26	0.00	93.53	0.48			94.13	0.00	96.68	0.00	97.52	0.00	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3775097298
94.61	0.07	94.16	0.01	91.44	0.18	93.54	0.01			94.34	0.21	96.68	0.00	97.52	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.914687602
94.68	0.06	94.16	0.00	91.83	0.39	93.54	0.00			94.34	0.00	96.68	0.00	97.52	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.1282700837
94.74	0.06	94.30	0.14	91.88	0.05	93.67	0.13			94.39	0.04	96.68	0.00	97.53	0.01	/workspace/coverage/default/33.chip_sw_all_escalation_resets.1517616518
94.79	0.05	94.36	0.07	92.03	0.15	93.67	0.00			94.48	0.10	96.68	0.00	97.53	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.481231639
94.84	0.05	94.36	0.00	92.11	0.08	93.67	0.00			94.50	0.02	96.68	0.00	97.73	0.20	/workspace/coverage/cover_reg_top/8.xbar_stress_all.3890435471
94.89	0.04	94.40	0.04	92.21	0.10	93.79	0.12			94.51	0.01	96.68	0.00	97.73	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.772517616
94.93	0.04	94.40	0.00	92.22	0.01	94.04	0.25			94.51	0.00	96.68	0.00	97.73	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1594940830
94.97	0.04	94.40	0.00	92.29	0.07	94.04	0.00			94.51	0.00	96.68	0.00	97.91	0.18	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.641851559
95.01	0.04	94.41	0.01	92.31	0.02	94.04	0.00			94.53	0.02	96.85	0.17	97.92	0.01	/workspace/coverage/default/75.chip_sw_all_escalation_resets.4114459315
95.05	0.04	94.44	0.03	92.31	0.01	94.04	0.01			94.54	0.01	97.03	0.17	97.93	0.01	/workspace/coverage/default/96.chip_sw_all_escalation_resets.3774684002
95.09	0.04	94.44	0.01	92.32	0.01	94.06	0.02			94.55	0.01	97.20	0.17	97.94	0.01	/workspace/coverage/default/31.chip_sw_all_escalation_resets.1642747210
95.12	0.04	94.45	0.01	92.34	0.01	94.06	0.00			94.56	0.01	97.38	0.17	97.96	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.80222921
95.15	0.03	94.48	0.03	92.38	0.04	94.14	0.08			94.60	0.04	97.38	0.00	97.96	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3998708261
95.19	0.03	94.48	0.00	92.38	0.00	94.34	0.20			94.60	0.00	97.38	0.00	97.96	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3418192565
95.22	0.03	94.48	0.00	92.45	0.07	94.34	0.00			94.60	0.00	97.38	0.00	98.07	0.12	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2835175905
95.25	0.03	94.48	0.00	92.45	0.00	94.34	0.01			94.60	0.00	97.55	0.17	98.07	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.439774011
95.27	0.03	94.49	0.01	92.47	0.02	94.47	0.13			94.60	0.00	97.55	0.00	98.07	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2586678360
95.30	0.03	94.49	0.00	92.62	0.15	94.47	0.00			94.60	0.00	97.55	0.00	98.07	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.572812725
95.32	0.02	94.49	0.00	92.77	0.14	94.47	0.00			94.60	0.00	97.55	0.00	98.07	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.2230600706
95.35	0.02	94.55	0.07	92.77	0.00	94.54	0.07			94.60	0.01	97.55	0.00	98.07	0.00	/workspace/coverage/default/2.chip_tap_straps_testunlock0.3352212382
95.37	0.02	94.55	0.00	92.77	0.00	94.54	0.00			94.60	0.00	97.55	0.00	98.21	0.14	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.248974687
95.39	0.02	94.55	0.00	92.77	0.01	94.54	0.00			94.60	0.00	97.55	0.00	98.34	0.13	/workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.230022697
95.42	0.02	94.58	0.02	92.83	0.06	94.55	0.01			94.65	0.05	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2712932345
95.44	0.02	94.58	0.00	92.83	0.00	94.66	0.12			94.65	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2860868642
95.46	0.02	94.61	0.03	92.88	0.05	94.67	0.01			94.68	0.02	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3786835511
95.47	0.02	94.64	0.03	92.92	0.05	94.68	0.01			94.70	0.02	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.217307028
95.49	0.02	94.64	0.00	92.92	0.00	94.78	0.10			94.70	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2844798114
95.51	0.02	94.69	0.05	92.94	0.01	94.79	0.01			94.73	0.03	97.55	0.00	98.34	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2706832410
95.52	0.02	94.69	0.00	93.04	0.10	94.79	0.00			94.73	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.4210993683
95.54	0.01	94.69	0.00	93.04	0.01	94.79	0.00			94.73	0.00	97.55	0.00	98.43	0.08	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.769279756
95.55	0.01	94.69	0.00	93.04	0.00	94.88	0.09			94.73	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1749759413
95.57	0.01	94.69	0.00	93.05	0.01	94.88	0.00			94.73	0.00	97.55	0.00	98.50	0.07	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.3371552651
95.58	0.01	94.72	0.04	93.08	0.02	94.88	0.00			94.75	0.02	97.55	0.00	98.50	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1770332054
95.59	0.01	94.72	0.00	93.15	0.07	94.88	0.00			94.75	0.00	97.55	0.00	98.50	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.2376054259
95.60	0.01	94.73	0.01	93.22	0.07	94.88	0.00			94.75	0.00	97.55	0.00	98.50	0.00	/workspace/coverage/cover_reg_top/10.chip_csr_rw.1194837898
95.62	0.01	94.73	0.00	93.28	0.05	94.88	0.00			94.75	0.00	97.55	0.00	98.51	0.01	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1495586070
95.63	0.01	94.76	0.03	93.30	0.02	94.88	0.00			94.76	0.01	97.55	0.00	98.51	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3110563667
95.64	0.01	94.76	0.00	93.30	0.00	94.94	0.06			94.76	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4232717683
95.65	0.01	94.76	0.00	93.35	0.06	94.94	0.00			94.76	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.3977578846
95.65	0.01	94.76	0.00	93.35	0.00	94.98	0.04			94.76	0.00	97.55	0.00	98.52	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.54394301
95.66	0.01	94.78	0.02	93.36	0.01	95.00	0.01			94.77	0.02	97.55	0.00	98.52	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3393232053
95.67	0.01	94.78	0.00	93.40	0.04	95.00	0.00			94.79	0.02	97.55	0.00	98.52	0.00	/workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1109443806
95.68	0.01	94.78	0.00	93.40	0.00	95.00	0.00			94.79	0.00	97.55	0.00	98.57	0.05	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2486461314
95.69	0.01	94.78	0.00	93.40	0.00	95.04	0.05			94.79	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2300539884
95.70	0.01	94.78	0.00	93.40	0.01	95.08	0.04			94.79	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1247594013
95.70	0.01	94.78	0.00	93.40	0.00	95.12	0.04			94.79	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2381828653
95.71	0.01	94.78	0.00	93.44	0.04	95.12	0.00			94.79	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.504815167
95.72	0.01	94.78	0.00	93.48	0.04	95.12	0.00			94.79	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3750316922
95.72	0.01	94.80	0.02	93.48	0.01	95.13	0.01			94.79	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.194398852
95.73	0.01	94.80	0.00	93.49	0.01	95.17	0.03			94.79	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2887646728
95.73	0.01	94.80	0.00	93.52	0.04	95.17	0.00			94.79	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/2.chip_sw_gpio.3677632281
95.74	0.01	94.80	0.00	93.52	0.00	95.17	0.00			94.79	0.00	97.55	0.00	98.60	0.04	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.489794637
95.74	0.01	94.80	0.00	93.52	0.00	95.17	0.00			94.79	0.00	97.55	0.00	98.64	0.04	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.1131453755
95.75	0.01	94.80	0.00	93.53	0.01	95.17	0.00			94.79	0.00	97.55	0.00	98.66	0.02	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1399133468
95.76	0.01	94.80	0.00	93.54	0.01	95.17	0.00			94.79	0.00	97.55	0.00	98.68	0.02	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.1366079240
95.76	0.01	94.80	0.00	93.55	0.02	95.17	0.00			94.79	0.00	97.55	0.00	98.70	0.01	/workspace/coverage/cover_reg_top/20.chip_tl_errors.3386320885
95.76	0.01	94.80	0.00	93.55	0.00	95.19	0.03			94.79	0.00	97.55	0.00	98.70	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1407157165
95.77	0.01	94.80	0.00	93.55	0.00	95.22	0.03			94.79	0.00	97.55	0.00	98.70	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1915765979
95.77	0.01	94.80	0.00	93.55	0.00	95.25	0.03			94.79	0.00	97.55	0.00	98.70	0.00	/workspace/coverage/default/1.chip_sw_kmac_entropy.1940638213
95.78	0.01	94.80	0.00	93.57	0.01	95.25	0.00			94.79	0.00	97.55	0.00	98.71	0.01	/workspace/coverage/cover_reg_top/56.xbar_stress_all.3074871073
95.78	0.01	94.80	0.00	93.57	0.00	95.25	0.00			94.79	0.00	97.55	0.00	98.73	0.02	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1071464815
95.79	0.01	94.80	0.00	93.57	0.00	95.25	0.00			94.79	0.00	97.55	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.409149855
95.79	0.01	94.80	0.00	93.57	0.00	95.25	0.00			94.79	0.00	97.55	0.00	98.78	0.02	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.47599602
95.79	0.01	94.80	0.00	93.57	0.00	95.27	0.02			94.79	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3339441253
95.80	0.01	94.80	0.01	93.58	0.01	95.28	0.01			94.79	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2128024260
95.80	0.01	94.80	0.00	93.60	0.02	95.28	0.00			94.79	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/14.chip_tl_errors.777755936
95.80	0.01	94.80	0.00	93.63	0.02	95.28	0.00			94.79	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.227947155
95.81	0.01	94.81	0.01	93.63	0.00	95.28	0.01			94.80	0.01	97.55	0.00	98.78	0.00	/workspace/coverage/default/4.chip_tap_straps_dev.2932705120
95.81	0.01	94.81	0.00	93.64	0.02	95.28	0.00			94.80	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1568632786
95.81	0.01	94.81	0.00	93.66	0.02	95.28	0.00			94.80	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1877426680
95.82	0.01	94.81	0.00	93.67	0.01	95.29	0.01			94.80	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1683561275
95.82	0.01	94.82	0.01	93.68	0.01	95.29	0.00			94.80	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3165001554
95.82	0.01	94.82	0.01	93.68	0.00	95.30	0.01			94.80	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2513112913
95.83	0.01	94.82	0.00	93.70	0.01	95.31	0.01			94.80	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2179521058
95.83	0.01	94.82	0.00	93.70	0.00	95.31	0.01			94.80	0.00	97.55	0.00	98.79	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2171037778
95.83	0.01	94.82	0.00	93.70	0.00	95.32	0.01			94.80	0.00	97.55	0.00	98.80	0.01	/workspace/coverage/default/85.chip_sw_all_escalation_resets.483372784
95.83	0.01	94.83	0.01	93.70	0.00	95.32	0.01			94.80	0.00	97.55	0.00	98.80	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.815744195
95.84	0.01	94.83	0.00	93.71	0.01	95.32	0.00			94.80	0.00	97.55	0.00	98.80	0.00	/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1499478126
95.84	0.01	94.83	0.00	93.72	0.01	95.32	0.00			94.80	0.00	97.55	0.00	98.80	0.00	/workspace/coverage/cover_reg_top/60.xbar_access_same_device.1176209932
95.84	0.01	94.83	0.00	93.74	0.01	95.32	0.00			94.80	0.00	97.55	0.00	98.80	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.462077752
95.84	0.01	94.83	0.00	93.75	0.01	95.32	0.00			94.80	0.00	97.55	0.00	98.80	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.27931283
95.85	0.01	94.83	0.00	93.75	0.00	95.32	0.01			94.80	0.00	97.55	0.00	98.81	0.01	/workspace/coverage/default/67.chip_sw_all_escalation_resets.3935789853
95.85	0.01	94.83	0.00	93.75	0.00	95.32	0.01			94.80	0.00	97.55	0.00	98.83	0.01	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.872617213
95.85	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.84	0.01	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2984843855
95.85	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.85	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2566362434
95.85	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.86	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.4127531792
95.86	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.87	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.1625509598
95.86	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.88	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2317455675
95.86	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.90	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.197985989
95.86	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.91	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2255511649
95.86	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.92	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.3723981503
95.87	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.93	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1707055191
95.87	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.94	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2871842132
95.87	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.95	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.2537203095
95.87	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.97	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.4008204433
95.87	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.98	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1920619379
95.88	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	98.99	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3697748703
95.88	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.137519384
95.88	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.01	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2465628269
95.88	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.02	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3641051009
95.88	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.04	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1389723445
95.88	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.05	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.2177439061
95.89	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.06	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.667634933
95.89	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.07	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1348079314
95.89	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.08	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.367793308
95.89	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1774111559
95.89	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.721602916
95.90	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.12	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2514809725
95.90	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.1074713342
95.90	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.14	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3729558805
95.90	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.15	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2470606609
95.90	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.17	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1158563270
95.91	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.18	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.687005225
95.91	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.19	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.2603133278
95.91	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.20	0.01	/workspace/coverage/default/30.chip_sw_all_escalation_resets.1657385850
95.91	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.21	0.01	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3471498844
95.91	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.22	0.01	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.992020835
95.92	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.24	0.01	/workspace/coverage/default/35.chip_sw_all_escalation_resets.38345291
95.92	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.25	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2305761420
95.92	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.26	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1195673776
95.92	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.27	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.3270207307
95.92	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.28	0.01	/workspace/coverage/default/38.chip_sw_all_escalation_resets.3970754473
95.93	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.30	0.01	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1461294871
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95.93	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.32	0.01	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4273036907
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95.94	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.37	0.01	/workspace/coverage/default/54.chip_sw_all_escalation_resets.2659076746
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95.95	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.42	0.01	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3309541726
95.95	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.44	0.01	/workspace/coverage/default/7.chip_sw_all_escalation_resets.2952445103
95.95	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.45	0.01	/workspace/coverage/default/72.chip_sw_all_escalation_resets.2161078009
95.95	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.46	0.01	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2178314018
95.96	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.47	0.01	/workspace/coverage/default/73.chip_sw_all_escalation_resets.3911765465
95.96	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.48	0.01	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3363534488
95.96	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2431496997
95.96	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/80.chip_sw_all_escalation_resets.607543165
95.96	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2595792307
95.97	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1128654810
95.97	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/88.chip_sw_all_escalation_resets.4183195207
95.97	0.01	94.83	0.00	93.75	0.00	95.32	0.00			94.80	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.517633853
95.97	0.01	94.83	0.00	93.76	0.01	95.32	0.00			94.81	0.01	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1108282347
95.97	0.01	94.83	0.00	93.77	0.01	95.32	0.00			94.81	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/3.chip_tl_errors.2874302905
95.97	0.01	94.83	0.00	93.78	0.01	95.32	0.00			94.81	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.121320822
95.98	0.01	94.83	0.00	93.79	0.01	95.32	0.00			94.81	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4200420473
95.98	0.01	94.83	0.00	93.80	0.01	95.32	0.00			94.81	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_gpio.16297799
95.98	0.01	94.83	0.00	93.81	0.01	95.32	0.00			94.81	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.482462345
95.98	0.01	94.84	0.01	93.81	0.00	95.33	0.01			94.81	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/22.chip_sw_all_escalation_resets.819606660
95.98	0.01	94.84	0.01	93.81	0.01	95.33	0.00			94.81	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4191677564
95.98	0.01	94.84	0.00	93.81	0.00	95.34	0.01			94.81	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.841217893
95.99	0.01	94.84	0.00	93.81	0.00	95.35	0.01			94.81	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3405308711
95.99	0.01	94.84	0.00	93.81	0.00	95.36	0.01			94.81	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4198158485
95.99	0.01	94.84	0.00	93.81	0.00	95.37	0.01			94.81	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.176723019
95.99	0.01	94.85	0.01	93.81	0.00	95.37	0.01			94.81	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_power_sleep_load.302727425
95.99	0.01	94.85	0.00	93.81	0.00	95.37	0.00			94.82	0.01	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.209974943
95.99	0.01	94.85	0.00	93.82	0.01	95.37	0.00			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/10.xbar_random.1287319258
95.99	0.01	94.85	0.00	93.83	0.01	95.37	0.00			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/21.xbar_same_source.1403221362
96.00	0.01	94.85	0.00	93.83	0.00	95.38	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.32879999
96.00	0.01	94.85	0.00	93.83	0.00	95.39	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3268528038
96.00	0.01	94.85	0.00	93.83	0.00	95.39	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1141570836
96.00	0.01	94.85	0.01	93.83	0.00	95.39	0.00			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3261781370
96.00	0.01	94.86	0.01	93.83	0.00	95.39	0.00			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.616743225
96.00	0.01	94.87	0.01	93.83	0.00	95.39	0.00			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.3285887505
96.00	0.01	94.87	0.00	93.83	0.00	95.40	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3287748997
96.00	0.01	94.87	0.00	93.83	0.00	95.40	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1604901925
96.00	0.01	94.87	0.00	93.83	0.00	95.41	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2637220591
96.00	0.01	94.87	0.00	93.83	0.00	95.41	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4249535403
96.01	0.01	94.87	0.00	93.83	0.01	95.41	0.00			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1006709240
96.01	0.01	94.87	0.00	93.83	0.01	95.41	0.00			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.410678766
96.01	0.01	94.87	0.00	93.84	0.01	95.41	0.00			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.3594005622
96.01	0.01	94.87	0.00	93.84	0.01	95.41	0.00			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.559431555
96.01	0.01	94.87	0.00	93.84	0.01	95.41	0.00			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.2438471757
96.01	0.01	94.87	0.00	93.85	0.01	95.41	0.00			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.787048448
96.01	0.01	94.87	0.00	93.85	0.01	95.41	0.00			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2484463856
96.01	0.01	94.87	0.00	93.86	0.01	95.41	0.00			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3050473931
96.01	0.01	94.87	0.00	93.86	0.00	95.42	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.2850436985
96.01	0.01	94.87	0.00	93.86	0.00	95.42	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3222197135
96.01	0.01	94.87	0.00	93.86	0.00	95.42	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2277478409
96.01	0.01	94.87	0.00	93.86	0.00	95.42	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3810756633
96.01	0.01	94.87	0.00	93.86	0.00	95.42	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2732326587
96.01	0.01	94.87	0.00	93.86	0.00	95.43	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1733149299
96.01	0.01	94.87	0.00	93.86	0.00	95.43	0.01			94.82	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.73713654

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3129760237
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.923083046
/workspace/coverage/cover_reg_top/0.chip_csr_rw.3547536347
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.946915454
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2986134868
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2310089944
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3173320515
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1729054392
/workspace/coverage/cover_reg_top/0.xbar_error_random.3789150289
/workspace/coverage/cover_reg_top/0.xbar_random.1040739981
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2488091882
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3871675119
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3553693207
/workspace/coverage/cover_reg_top/0.xbar_same_source.3464917940
/workspace/coverage/cover_reg_top/0.xbar_smoke.873891428
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2246014878
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3503593616
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2233550262
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2491581723
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.452371199
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3015938876
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.81459412
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1284968982
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.945958981
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1582948557
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.23853928
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.4078477827
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.4078256778
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.810222752
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.789508102
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.373845221
/workspace/coverage/cover_reg_top/1.xbar_error_random.1889261624
/workspace/coverage/cover_reg_top/1.xbar_random.2689914952
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1850695351
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3922186545
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1256492654
/workspace/coverage/cover_reg_top/1.xbar_same_source.1496788811
/workspace/coverage/cover_reg_top/1.xbar_smoke.2235996437
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.4234250453
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3028628425
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2287773528
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1672559888
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3025763738
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2436852850
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.744515038
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3493685245
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1278799680
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.8104408
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3360093200
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3534044649
/workspace/coverage/cover_reg_top/10.xbar_error_random.1093054956
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2904311158
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2122172519
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3458273582
/workspace/coverage/cover_reg_top/10.xbar_same_source.2100552515
/workspace/coverage/cover_reg_top/10.xbar_smoke.2331773754
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.4251832803
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1420155319
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1307528505
/workspace/coverage/cover_reg_top/10.xbar_stress_all.706155743
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.946421258
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1206757936
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2909370516
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1233236699
/workspace/coverage/cover_reg_top/11.chip_csr_rw.4028429709
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1269968492
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1637717181
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1799379733
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1911820677
/workspace/coverage/cover_reg_top/11.xbar_error_random.441041628
/workspace/coverage/cover_reg_top/11.xbar_random.3988122125
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.316733393
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3072038226
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1685408897
/workspace/coverage/cover_reg_top/11.xbar_same_source.1784786158
/workspace/coverage/cover_reg_top/11.xbar_smoke.3220920657
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3772044890
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3491823280
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1442845123
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3236685114
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2917390409
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.4054997502
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.465171280
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3062095243
/workspace/coverage/cover_reg_top/12.chip_csr_rw.29962807
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.4122027267
/workspace/coverage/cover_reg_top/12.chip_tl_errors.4211084611
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1926015199
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1977693355
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1173627146
/workspace/coverage/cover_reg_top/12.xbar_error_random.2501832862
/workspace/coverage/cover_reg_top/12.xbar_random.744297073
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3227176187
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2796760000
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1549846920
/workspace/coverage/cover_reg_top/12.xbar_same_source.2453912610
/workspace/coverage/cover_reg_top/12.xbar_smoke.394840880
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.4197961102
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2122926351
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2197528991
/workspace/coverage/cover_reg_top/12.xbar_stress_all.908874574
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.953702295
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3376332535
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.921026242
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.4293041009
/workspace/coverage/cover_reg_top/13.chip_tl_errors.489162172
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3803132637
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.4285790106
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3405037499
/workspace/coverage/cover_reg_top/13.xbar_error_random.2133388252
/workspace/coverage/cover_reg_top/13.xbar_random.2132499365
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/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.330796783
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/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3385648197
/workspace/coverage/default/2.chip_sw_rv_timer_irq.2500930751
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4247904169
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2130254953
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2567921308
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2995409826
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1626181719
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/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1449587280
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/workspace/coverage/default/32.chip_sw_all_escalation_resets.1300831744
/workspace/coverage/default/34.chip_sw_all_escalation_resets.46615461
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3793121172
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3646686091
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.234071028
/workspace/coverage/default/39.chip_sw_all_escalation_resets.753233982
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3215047031
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.4140824247
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3189821428
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3020142858
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4127039578
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2922789946
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2218363391
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2631374876
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2515831512
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/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.20899294
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/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.545431082
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/workspace/coverage/default/48.chip_sw_all_escalation_resets.2286986078
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2870540521
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3853701546
/workspace/coverage/default/5.chip_sw_all_escalation_resets.1953496308
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.114591733
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3734873005
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3627803404
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1685728395
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3797847011
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1790052953
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4097744355
/workspace/coverage/default/51.chip_sw_all_escalation_resets.928162478
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.922021100
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1931442914
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3040136121
/workspace/coverage/default/53.chip_sw_all_escalation_resets.261957147
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2756649924
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3116552714
/workspace/coverage/default/55.chip_sw_all_escalation_resets.91068901
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4123388994
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2787399243
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1943596678
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1480913430
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3465589574
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.522922532
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1331907189
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.928373696
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3410913315
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2451252018
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1710626726
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2761385799
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3910528473
/workspace/coverage/default/61.chip_sw_all_escalation_resets.776085767
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2613136232
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3251415707
/workspace/coverage/default/63.chip_sw_all_escalation_resets.424053552
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2718459367
/workspace/coverage/default/64.chip_sw_all_escalation_resets.252654121
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3813012585
/workspace/coverage/default/65.chip_sw_all_escalation_resets.64439982
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.342204015
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3851861098
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1363014910
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2935823762
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3925843844
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3039451531
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2819560654
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1704173434
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3833760950
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.735798324
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1997220039
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2821278997
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.258839209
/workspace/coverage/default/71.chip_sw_all_escalation_resets.1343375547
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2455379474
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2461135776
/workspace/coverage/default/76.chip_sw_all_escalation_resets.4072276050
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1352639104
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2126178604
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1331482434
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3513918040
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3478602954
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2938113844
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1452681107
/workspace/coverage/default/8.chip_sw_all_escalation_resets.203813876
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.945624009
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.383949591
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3783882736
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1382744739
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2730889766
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2262260102
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1857281120
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3706617465
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.698776593
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3501692695
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1873964981
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1334351947
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2792254258
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.522048031
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3827290831
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1163860566
/workspace/coverage/default/9.chip_sw_all_escalation_resets.948138410
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.680645520
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.71875662
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1006128054
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3681099810
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2740070052
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3248547379
/workspace/coverage/default/93.chip_sw_all_escalation_resets.4263090108
/workspace/coverage/default/94.chip_sw_all_escalation_resets.171402804
/workspace/coverage/default/95.chip_sw_all_escalation_resets.684695713
/workspace/coverage/default/97.chip_sw_all_escalation_resets.866834007
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1003286980
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1706705503
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2756324963
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.759659345
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4082107623
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.6397169
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.671275549
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.891775868
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3318653317
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.102210832

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Total test records in report: 2900

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3189821428			Jul 02 11:26:33 AM PDT 24	Jul 02 11:42:18 AM PDT 24	5388214412 ps
T5	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2501666352			Jul 02 11:15:10 AM PDT 24	Jul 02 11:20:18 AM PDT 24	2041949658 ps
T1	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2839271323			Jul 02 11:01:53 AM PDT 24	Jul 02 11:10:05 AM PDT 24	7633969544 ps
T18	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3416710041			Jul 02 11:30:57 AM PDT 24	Jul 02 12:27:54 PM PDT 24	15142756492 ps
T17	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3016758104			Jul 02 10:59:33 AM PDT 24	Jul 02 11:31:12 AM PDT 24	12620136692 ps
T19	/workspace/coverage/default/1.chip_jtag_mem_access.201308257			Jul 02 11:04:17 AM PDT 24	Jul 02 11:28:27 AM PDT 24	13788868964 ps
T89	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2586678360			Jul 02 11:16:58 AM PDT 24	Jul 02 11:38:48 AM PDT 24	8545764215 ps
T20	/workspace/coverage/default/0.chip_jtag_mem_access.754491951			Jul 02 10:52:25 AM PDT 24	Jul 02 11:17:11 AM PDT 24	14028648340 ps
T56	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1084322173			Jul 02 11:29:21 AM PDT 24	Jul 02 12:21:52 PM PDT 24	14760867336 ps
T57	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.73713654			Jul 02 11:08:16 AM PDT 24	Jul 02 12:51:48 PM PDT 24	24132257512 ps
T45	/workspace/coverage/default/33.chip_sw_all_escalation_resets.1517616518			Jul 02 11:31:02 AM PDT 24	Jul 02 11:39:16 AM PDT 24	4850527994 ps
T103	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2457028822			Jul 02 11:25:46 AM PDT 24	Jul 02 11:42:36 AM PDT 24	7171666546 ps
T114	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1922668761			Jul 02 11:09:00 AM PDT 24	Jul 02 11:27:20 AM PDT 24	16289328321 ps
T84	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2515482068			Jul 02 11:35:34 AM PDT 24	Jul 02 11:41:06 AM PDT 24	3687918280 ps
T93	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.872617213			Jul 02 11:33:57 AM PDT 24	Jul 02 11:40:13 AM PDT 24	3967084028 ps
T94	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.4057322960			Jul 02 11:08:14 AM PDT 24	Jul 02 12:21:55 PM PDT 24	15185892020 ps
T95	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2502492225			Jul 02 11:18:45 AM PDT 24	Jul 02 11:28:21 AM PDT 24	19291053280 ps
T59	/workspace/coverage/default/1.chip_tap_straps_dev.486303098			Jul 02 11:10:58 AM PDT 24	Jul 02 11:14:04 AM PDT 24	3022029902 ps
T96	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.992020835			Jul 02 11:32:37 AM PDT 24	Jul 02 11:40:43 AM PDT 24	3730623424 ps
T97	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.798605109			Jul 02 11:12:29 AM PDT 24	Jul 02 11:17:06 AM PDT 24	3168109230 ps
T98	/workspace/coverage/default/90.chip_sw_all_escalation_resets.3681099810			Jul 02 11:36:06 AM PDT 24	Jul 02 11:48:14 AM PDT 24	4806273352 ps
T99	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.963147148			Jul 02 11:22:58 AM PDT 24	Jul 02 11:40:10 AM PDT 24	7884009863 ps
T100	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1594940830			Jul 02 11:20:44 AM PDT 24	Jul 02 11:39:58 AM PDT 24	8623191894 ps
T295	/workspace/coverage/default/85.chip_sw_all_escalation_resets.483372784			Jul 02 11:36:08 AM PDT 24	Jul 02 11:48:20 AM PDT 24	5502950940 ps
T296	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.841217893			Jul 02 10:59:23 AM PDT 24	Jul 02 11:03:03 AM PDT 24	3042919144 ps
T297	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3507445631			Jul 02 11:11:14 AM PDT 24	Jul 02 11:18:14 AM PDT 24	3398073312 ps
T298	/workspace/coverage/default/18.chip_sw_all_escalation_resets.1909698937			Jul 02 11:29:59 AM PDT 24	Jul 02 11:46:09 AM PDT 24	5737004236 ps
T299	/workspace/coverage/default/1.chip_sw_example_rom.1312960058			Jul 02 11:04:08 AM PDT 24	Jul 02 11:06:07 AM PDT 24	3258103920 ps
T300	/workspace/coverage/default/9.chip_sw_all_escalation_resets.948138410			Jul 02 11:28:26 AM PDT 24	Jul 02 11:38:20 AM PDT 24	4893054104 ps
T301	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.3471610152			Jul 02 11:19:37 AM PDT 24	Jul 02 11:25:45 AM PDT 24	3238353096 ps
T302	/workspace/coverage/default/97.chip_sw_all_escalation_resets.866834007			Jul 02 11:37:23 AM PDT 24	Jul 02 11:48:58 AM PDT 24	6238193432 ps
T30	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3998708261			Jul 02 10:59:50 AM PDT 24	Jul 02 01:21:37 PM PDT 24	31337735384 ps
T73	/workspace/coverage/default/3.chip_tap_straps_prod.1288296931			Jul 02 11:25:40 AM PDT 24	Jul 02 11:51:58 AM PDT 24	15128948930 ps
T210	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1374048210			Jul 02 11:04:20 AM PDT 24	Jul 02 11:07:37 AM PDT 24	2068885828 ps
T442	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.17827543			Jul 02 11:03:13 AM PDT 24	Jul 02 11:06:35 AM PDT 24	2023315772 ps
T203	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3460187695			Jul 02 11:17:10 AM PDT 24	Jul 02 11:24:41 AM PDT 24	2997796209 ps
T448	/workspace/coverage/default/1.chip_sw_kmac_entropy.1940638213			Jul 02 11:05:17 AM PDT 24	Jul 02 11:09:47 AM PDT 24	2406579968 ps
T171	/workspace/coverage/default/0.rom_e2e_asm_init_dev.2184301557			Jul 02 11:08:08 AM PDT 24	Jul 02 12:17:49 PM PDT 24	15106330280 ps
T400	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3392672350			Jul 02 11:06:26 AM PDT 24	Jul 02 12:08:05 PM PDT 24	14872573760 ps
T305	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3478602954			Jul 02 11:37:14 AM PDT 24	Jul 02 11:43:04 AM PDT 24	4225678862 ps
T181	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2465120182			Jul 02 11:01:26 AM PDT 24	Jul 02 11:13:59 AM PDT 24	5412784112 ps
T928	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1335942297			Jul 02 11:14:34 AM PDT 24	Jul 02 11:19:37 AM PDT 24	2530277784 ps
T396	/workspace/coverage/default/56.chip_sw_all_escalation_resets.2787399243			Jul 02 11:34:00 AM PDT 24	Jul 02 11:43:05 AM PDT 24	6103209840 ps
T31	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1426944830			Jul 02 11:07:44 AM PDT 24	Jul 02 11:47:19 AM PDT 24	22229373760 ps
T74	/workspace/coverage/default/4.chip_tap_straps_dev.2932705120			Jul 02 11:26:18 AM PDT 24	Jul 02 11:37:02 AM PDT 24	6661118701 ps
T148	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1088320576			Jul 02 11:04:33 AM PDT 24	Jul 02 11:09:37 AM PDT 24	3214014520 ps
T109	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3757134937			Jul 02 11:28:59 AM PDT 24	Jul 02 11:34:42 AM PDT 24	3353052257 ps
T58	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.2413716909			Jul 02 11:20:50 AM PDT 24	Jul 02 11:29:45 AM PDT 24	4402609728 ps
T348	/workspace/coverage/default/28.chip_sw_all_escalation_resets.3490843612			Jul 02 11:31:29 AM PDT 24	Jul 02 11:43:16 AM PDT 24	5425854712 ps
T85	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3805267473			Jul 02 11:00:08 AM PDT 24	Jul 02 11:05:27 AM PDT 24	3605104216 ps
T69	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4253196732			Jul 02 11:00:41 AM PDT 24	Jul 02 11:12:24 AM PDT 24	4742110384 ps
T75	/workspace/coverage/default/1.chip_tap_straps_prod.218634683			Jul 02 11:11:10 AM PDT 24	Jul 02 11:39:20 AM PDT 24	17462562087 ps
T703	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2795338022			Jul 02 11:04:50 AM PDT 24	Jul 02 11:14:56 AM PDT 24	5394141432 ps
T237	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4273036907			Jul 02 11:32:55 AM PDT 24	Jul 02 11:40:18 AM PDT 24	3514028200 ps
T139	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3805538995			Jul 02 11:26:40 AM PDT 24	Jul 02 11:38:31 AM PDT 24	5029539200 ps
T373	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2456832311			Jul 02 11:28:54 AM PDT 24	Jul 02 12:31:10 PM PDT 24	15713526616 ps
T21	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3512912499			Jul 02 11:05:40 AM PDT 24	Jul 02 11:10:09 AM PDT 24	3083615764 ps
T46	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.194398852			Jul 02 11:02:55 AM PDT 24	Jul 02 11:08:23 AM PDT 24	2753338814 ps
T238	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1790479247			Jul 02 11:25:28 AM PDT 24	Jul 02 11:37:38 AM PDT 24	5734458532 ps
T110	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.280579799			Jul 02 11:28:54 AM PDT 24	Jul 02 11:38:58 AM PDT 24	5295153219 ps
T733	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3646686091			Jul 02 11:33:21 AM PDT 24	Jul 02 11:41:23 AM PDT 24	3520560824 ps
T402	/workspace/coverage/default/2.chip_sw_kmac_app_rom.2885604614			Jul 02 11:20:48 AM PDT 24	Jul 02 11:26:40 AM PDT 24	2898033744 ps
T118	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3268528038			Jul 02 11:00:11 AM PDT 24	Jul 02 11:38:19 AM PDT 24	9199863110 ps
T534	/workspace/coverage/default/95.chip_sw_all_escalation_resets.684695713			Jul 02 11:36:31 AM PDT 24	Jul 02 11:45:50 AM PDT 24	4204694936 ps
T374	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2876062129			Jul 02 11:07:35 AM PDT 24	Jul 02 12:22:46 PM PDT 24	15922247358 ps
T723	/workspace/coverage/default/2.chip_sw_aes_enc.3384616771			Jul 02 11:18:38 AM PDT 24	Jul 02 11:24:23 AM PDT 24	3605561592 ps
T70	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3796105877			Jul 02 11:11:37 AM PDT 24	Jul 02 11:19:57 AM PDT 24	4984553518 ps
T316	/workspace/coverage/default/1.chip_sw_hmac_enc.2560633311			Jul 02 11:11:29 AM PDT 24	Jul 02 11:16:15 AM PDT 24	3620604656 ps
T929	/workspace/coverage/default/2.chip_sw_hmac_smoketest.3724123176			Jul 02 11:24:31 AM PDT 24	Jul 02 11:30:42 AM PDT 24	2852021564 ps
T930	/workspace/coverage/default/2.chip_sw_hmac_multistream.1446305073			Jul 02 11:20:11 AM PDT 24	Jul 02 11:49:13 AM PDT 24	7765280920 ps
T317	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2578038903			Jul 02 11:04:14 AM PDT 24	Jul 02 11:13:43 AM PDT 24	4416874168 ps
T6	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3393232053			Jul 02 11:04:05 AM PDT 24	Jul 02 11:15:35 AM PDT 24	4147874808 ps
T437	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.762210054			Jul 02 11:09:58 AM PDT 24	Jul 02 11:16:20 AM PDT 24	3815633686 ps
T438	/workspace/coverage/default/1.chip_sw_csrng_kat_test.1922863231			Jul 02 11:08:24 AM PDT 24	Jul 02 11:11:58 AM PDT 24	2897744404 ps
T439	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.291262367			Jul 02 11:22:14 AM PDT 24	Jul 02 11:25:54 AM PDT 24	2509440072 ps
T153	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1710626726			Jul 02 11:35:53 AM PDT 24	Jul 02 11:41:59 AM PDT 24	3497220344 ps
T211	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3611663532			Jul 02 11:09:23 AM PDT 24	Jul 02 11:41:01 AM PDT 24	7477697848 ps
T168	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.4231262102			Jul 02 11:05:45 AM PDT 24	Jul 02 11:28:29 AM PDT 24	8549131990 ps
T307	/workspace/coverage/default/31.chip_sw_all_escalation_resets.1642747210			Jul 02 11:35:13 AM PDT 24	Jul 02 11:45:05 AM PDT 24	4568984824 ps
T440	/workspace/coverage/default/40.chip_sw_all_escalation_resets.101858393			Jul 02 11:32:37 AM PDT 24	Jul 02 11:47:10 AM PDT 24	5568737716 ps
T239	/workspace/coverage/default/96.chip_sw_all_escalation_resets.3774684002			Jul 02 11:35:52 AM PDT 24	Jul 02 11:45:50 AM PDT 24	4777140552 ps
T204	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2793006745			Jul 02 11:17:49 AM PDT 24	Jul 02 11:29:42 AM PDT 24	4426136757 ps
T263	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2369403750			Jul 02 11:17:00 AM PDT 24	Jul 02 11:30:12 AM PDT 24	10422107054 ps
T264	/workspace/coverage/default/21.chip_sw_all_escalation_resets.667634933			Jul 02 11:32:39 AM PDT 24	Jul 02 11:42:49 AM PDT 24	4828096744 ps
T265	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1920619379			Jul 02 11:29:31 AM PDT 24	Jul 02 11:36:43 AM PDT 24	3433883040 ps
T242	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2166506052			Jul 02 11:05:49 AM PDT 24	Jul 02 11:11:21 AM PDT 24	5494045080 ps
T32	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.373147032			Jul 02 11:08:38 AM PDT 24	Jul 02 12:02:49 PM PDT 24	20389596583 ps
T266	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2465628269			Jul 02 11:20:32 AM PDT 24	Jul 02 11:28:56 AM PDT 24	3630347384 ps
T267	/workspace/coverage/default/54.chip_sw_all_escalation_resets.2659076746			Jul 02 11:32:42 AM PDT 24	Jul 02 11:45:42 AM PDT 24	5209482740 ps
T268	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.492946661			Jul 02 11:08:17 AM PDT 24	Jul 02 11:21:26 AM PDT 24	4330870360 ps
T690	/workspace/coverage/default/2.chip_sw_aes_masking_off.3764492350			Jul 02 11:19:22 AM PDT 24	Jul 02 11:24:16 AM PDT 24	3169810349 ps
T7	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.140449966			Jul 02 11:22:53 AM PDT 24	Jul 02 11:30:40 AM PDT 24	4595803488 ps
T728	/workspace/coverage/default/44.chip_sw_all_escalation_resets.3488090849			Jul 02 11:35:02 AM PDT 24	Jul 02 11:43:15 AM PDT 24	5712786828 ps
T63	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3344520813			Jul 02 11:06:14 AM PDT 24	Jul 02 11:27:00 AM PDT 24	9516115270 ps
T88	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1568632786			Jul 02 10:58:09 AM PDT 24	Jul 02 03:02:50 PM PDT 24	77700437762 ps
T344	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3110841828			Jul 02 11:23:48 AM PDT 24	Jul 02 11:29:39 AM PDT 24	2525527542 ps
T729	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3215047031			Jul 02 11:26:54 AM PDT 24	Jul 02 11:34:13 AM PDT 24	7118315208 ps
T163	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2645348314			Jul 02 11:11:38 AM PDT 24	Jul 02 12:39:57 PM PDT 24	18457389904 ps
T155	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2381828653			Jul 02 10:59:39 AM PDT 24	Jul 02 11:01:26 AM PDT 24	2413081046 ps
T405	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3116552714			Jul 02 11:32:55 AM PDT 24	Jul 02 11:38:29 AM PDT 24	3903655928 ps
T119	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3186120198			Jul 02 11:08:13 AM PDT 24	Jul 02 12:14:41 PM PDT 24	17304080540 ps
T702	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1093899931			Jul 02 10:59:16 AM PDT 24	Jul 02 11:06:08 AM PDT 24	6626323867 ps
T2	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3347690323			Jul 02 11:21:41 AM PDT 24	Jul 02 11:47:38 AM PDT 24	20335257680 ps
T240	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1193817104			Jul 02 11:16:05 AM PDT 24	Jul 02 11:25:22 AM PDT 24	5508608728 ps
T736	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.924101839			Jul 02 10:59:03 AM PDT 24	Jul 02 11:24:51 AM PDT 24	7483634380 ps
T742	/workspace/coverage/default/53.chip_sw_all_escalation_resets.261957147			Jul 02 11:33:48 AM PDT 24	Jul 02 11:43:19 AM PDT 24	5764960308 ps
T931	/workspace/coverage/default/2.chip_tap_straps_dev.2495030212			Jul 02 11:22:08 AM PDT 24	Jul 02 11:25:07 AM PDT 24	2734479012 ps
T278	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3734873005			Jul 02 11:26:53 AM PDT 24	Jul 02 11:37:17 AM PDT 24	6384944832 ps
T303	/workspace/coverage/default/2.chip_sw_uart_tx_rx.2029941464			Jul 02 11:14:39 AM PDT 24	Jul 02 11:26:30 AM PDT 24	4320061636 ps
T932	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1287314292			Jul 02 11:11:15 AM PDT 24	Jul 02 12:23:24 PM PDT 24	15464427572 ps
T27	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3783882736			Jul 02 11:27:48 AM PDT 24	Jul 02 11:36:54 AM PDT 24	3952542704 ps
T933	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3520864568			Jul 02 11:00:12 AM PDT 24	Jul 02 11:06:37 AM PDT 24	3497813814 ps
T120	/workspace/coverage/default/0.chip_sw_edn_sw_mode.2962049238			Jul 02 11:00:57 AM PDT 24	Jul 02 11:23:01 AM PDT 24	6526750060 ps
T329	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3385648197			Jul 02 11:25:13 AM PDT 24	Jul 02 11:29:11 AM PDT 24	2360682682 ps
T28	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1959449668			Jul 02 11:25:37 AM PDT 24	Jul 02 11:37:13 AM PDT 24	4786816010 ps
T164	/workspace/coverage/default/1.chip_sival_flash_info_access.2695557008			Jul 02 11:05:48 AM PDT 24	Jul 02 11:12:55 AM PDT 24	3164855384 ps
T734	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3040136121			Jul 02 11:34:02 AM PDT 24	Jul 02 11:39:55 AM PDT 24	3456939818 ps
T724	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2595792307			Jul 02 11:35:29 AM PDT 24	Jul 02 11:40:59 AM PDT 24	3840036566 ps
T254	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2949953547			Jul 02 11:19:13 AM PDT 24	Jul 02 11:31:09 AM PDT 24	3877332864 ps
T121	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3623858737			Jul 02 11:17:29 AM PDT 24	Jul 02 11:26:38 AM PDT 24	8765399508 ps
T304	/workspace/coverage/default/1.chip_plic_all_irqs_20.821281210			Jul 02 11:10:13 AM PDT 24	Jul 02 11:24:13 AM PDT 24	5210330808 ps
T107	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2843645073			Jul 02 11:24:22 AM PDT 24	Jul 02 11:58:41 AM PDT 24	12295051300 ps
T64	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.542528052			Jul 02 11:29:19 AM PDT 24	Jul 02 11:39:07 AM PDT 24	6479683743 ps
T766	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.841856849			Jul 02 11:33:06 AM PDT 24	Jul 02 11:41:09 AM PDT 24	3659936896 ps
T732	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1390988022			Jul 02 11:08:00 AM PDT 24	Jul 02 11:21:33 AM PDT 24	7540409496 ps
T752	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.389989816			Jul 02 11:00:55 AM PDT 24	Jul 02 11:20:34 AM PDT 24	7530359856 ps
T328	/workspace/coverage/default/0.chip_sw_otbn_randomness.2619598136			Jul 02 10:58:40 AM PDT 24	Jul 02 11:13:58 AM PDT 24	6505299800 ps
T934	/workspace/coverage/default/0.chip_sw_example_flash.2936837612			Jul 02 10:58:05 AM PDT 24	Jul 02 11:02:31 AM PDT 24	3295353320 ps
T169	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.150277143			Jul 02 11:15:44 AM PDT 24	Jul 02 11:40:21 AM PDT 24	7825696362 ps
T257	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3451692205			Jul 02 11:19:35 AM PDT 24	Jul 02 01:14:36 PM PDT 24	29207480056 ps
T388	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.4046946369			Jul 02 11:22:12 AM PDT 24	Jul 02 11:27:27 AM PDT 24	3572381792 ps
T108	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3418192565			Jul 02 10:59:30 AM PDT 24	Jul 02 11:18:11 AM PDT 24	6870482528 ps
T183	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1989618962			Jul 02 11:13:12 AM PDT 24	Jul 02 11:17:25 AM PDT 24	2931169476 ps
T259	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3174459686			Jul 02 11:00:10 AM PDT 24	Jul 02 11:23:47 AM PDT 24	7081834380 ps
T60	/workspace/coverage/default/1.chip_sw_alert_test.3383454398			Jul 02 11:08:43 AM PDT 24	Jul 02 11:14:38 AM PDT 24	3395872416 ps
T289	/workspace/coverage/default/0.chip_sw_kmac_idle.254588343			Jul 02 11:01:33 AM PDT 24	Jul 02 11:06:22 AM PDT 24	2433806264 ps
T158	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3775097298			Jul 02 11:36:50 AM PDT 24	Jul 02 11:45:43 AM PDT 24	4924480732 ps
T290	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1947710306			Jul 02 11:20:50 AM PDT 24	Jul 02 11:42:12 AM PDT 24	12629064496 ps
T291	/workspace/coverage/default/0.chip_sw_hmac_multistream.1714918050			Jul 02 11:00:07 AM PDT 24	Jul 02 11:28:07 AM PDT 24	7116008100 ps
T292	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3787243965			Jul 02 11:09:50 AM PDT 24	Jul 02 11:13:09 AM PDT 24	2859404080 ps
T51	/workspace/coverage/default/2.chip_sw_spi_device_tpm.3821393640			Jul 02 11:15:20 AM PDT 24	Jul 02 11:22:09 AM PDT 24	3269855787 ps
T293	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3367963475			Jul 02 10:58:09 AM PDT 24	Jul 02 11:08:54 AM PDT 24	7704678500 ps
T90	/workspace/coverage/default/67.chip_sw_all_escalation_resets.3935789853			Jul 02 11:33:41 AM PDT 24	Jul 02 11:43:37 AM PDT 24	4929380920 ps
T726	/workspace/coverage/default/45.chip_sw_all_escalation_resets.228496575			Jul 02 11:33:08 AM PDT 24	Jul 02 11:41:04 AM PDT 24	4614997160 ps
T258	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.114591733			Jul 02 11:27:54 AM PDT 24	Jul 02 12:37:54 PM PDT 24	18810620436 ps
T935	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4101534811			Jul 02 10:58:13 AM PDT 24	Jul 02 11:06:15 AM PDT 24	5102247756 ps
T936	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2059491782			Jul 02 10:59:16 AM PDT 24	Jul 02 11:10:29 AM PDT 24	9931465940 ps
T154	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1768713898			Jul 02 11:30:28 AM PDT 24	Jul 02 11:36:07 AM PDT 24	4123044152 ps
T214	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3198597143			Jul 02 10:59:26 AM PDT 24	Jul 02 11:33:00 AM PDT 24	10964297316 ps
T937	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.241924054			Jul 02 11:04:30 AM PDT 24	Jul 02 11:23:25 AM PDT 24	6114611366 ps
T748	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2521618563			Jul 02 11:26:08 AM PDT 24	Jul 02 11:37:44 AM PDT 24	5778773364 ps
T111	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3203838506			Jul 02 11:04:05 AM PDT 24	Jul 02 11:15:44 AM PDT 24	5014827693 ps
T530	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.354209572			Jul 02 11:19:23 AM PDT 24	Jul 02 11:36:22 AM PDT 24	4876979398 ps
T727	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1241411096			Jul 02 11:21:25 AM PDT 24	Jul 02 11:53:49 AM PDT 24	26703285180 ps
T938	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3927306524			Jul 02 11:26:10 AM PDT 24	Jul 02 11:51:45 AM PDT 24	8208758945 ps
T939	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2513112913			Jul 02 11:05:24 AM PDT 24	Jul 02 11:25:05 AM PDT 24	8584894492 ps
T940	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3640486753			Jul 02 11:11:28 AM PDT 24	Jul 02 11:50:22 AM PDT 24	24476699640 ps
T165	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1773053475			Jul 02 11:16:41 AM PDT 24	Jul 02 11:31:41 AM PDT 24	4558605936 ps
T375	/workspace/coverage/default/2.rom_e2e_asm_init_dev.3219250132			Jul 02 11:27:17 AM PDT 24	Jul 02 12:24:34 PM PDT 24	15160808433 ps
T54	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3906199616			Jul 02 11:08:04 AM PDT 24	Jul 02 12:23:08 PM PDT 24	14538822360 ps
T24	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3562738972			Jul 02 11:04:56 AM PDT 24	Jul 02 11:11:36 AM PDT 24	3125157000 ps
T104	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1141570836			Jul 02 11:24:33 AM PDT 24	Jul 02 04:55:57 PM PDT 24	148367207304 ps
T22	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2265117963			Jul 02 11:16:43 AM PDT 24	Jul 02 11:23:55 AM PDT 24	3093949607 ps
T349	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.32879999			Jul 02 11:00:52 AM PDT 24	Jul 02 11:07:32 AM PDT 24	18427577716 ps
T692	/workspace/coverage/default/20.chip_sw_all_escalation_resets.2177439061			Jul 02 11:32:04 AM PDT 24	Jul 02 11:41:18 AM PDT 24	4452908536 ps
T175	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2707639191			Jul 02 11:00:42 AM PDT 24	Jul 02 11:37:13 AM PDT 24	20617691347 ps
T184	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.4215141916			Jul 02 11:10:18 AM PDT 24	Jul 02 11:26:49 AM PDT 24	8989920307 ps
T755	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.20899294			Jul 02 11:31:43 AM PDT 24	Jul 02 11:39:31 AM PDT 24	3696202400 ps
T341	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2712932345			Jul 02 10:59:48 AM PDT 24	Jul 02 11:11:43 AM PDT 24	4674311096 ps
T52	/workspace/coverage/default/0.chip_sw_spi_device_tpm.2834000999			Jul 02 10:58:51 AM PDT 24	Jul 02 11:05:21 AM PDT 24	3578074744 ps
T308	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2756649924			Jul 02 11:34:40 AM PDT 24	Jul 02 11:41:29 AM PDT 24	3674893352 ps
T941	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1532258156			Jul 02 11:00:45 AM PDT 24	Jul 02 11:06:39 AM PDT 24	6955040080 ps
T65	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3627803404			Jul 02 11:28:37 AM PDT 24	Jul 02 11:44:56 AM PDT 24	9544280537 ps
T760	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2171037778			Jul 02 11:32:33 AM PDT 24	Jul 02 11:42:18 AM PDT 24	5119096648 ps
T182	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.896934366			Jul 02 11:09:16 AM PDT 24	Jul 02 11:18:13 AM PDT 24	4234191525 ps
T306	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.514301783			Jul 02 10:59:23 AM PDT 24	Jul 02 11:10:19 AM PDT 24	4718647816 ps
T29	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2451252018			Jul 02 11:28:49 AM PDT 24	Jul 02 11:39:10 AM PDT 24	4065364200 ps
T753	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1331907189			Jul 02 11:30:50 AM PDT 24	Jul 02 11:36:58 AM PDT 24	3712170432 ps
T212	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2354119753			Jul 02 11:15:45 AM PDT 24	Jul 02 11:31:55 AM PDT 24	5236095660 ps
T216	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3563571552			Jul 02 11:09:08 AM PDT 24	Jul 02 11:41:54 AM PDT 24	8489110524 ps
T942	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.996102939			Jul 02 11:11:07 AM PDT 24	Jul 02 11:35:29 AM PDT 24	12554509832 ps
T338	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.904170599			Jul 02 11:04:51 AM PDT 24	Jul 02 11:29:38 AM PDT 24	9507173640 ps
T112	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1190403183			Jul 02 11:20:45 AM PDT 24	Jul 02 11:29:11 AM PDT 24	4288142692 ps
T381	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2695006421			Jul 02 10:59:29 AM PDT 24	Jul 02 11:04:34 AM PDT 24	3383401848 ps
T176	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3136918863			Jul 02 11:05:22 AM PDT 24	Jul 02 11:11:12 AM PDT 24	4771824620 ps
T55	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.1691251939			Jul 02 11:18:34 AM PDT 24	Jul 02 12:29:08 PM PDT 24	14891384980 ps
T25	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1739160699			Jul 02 11:15:29 AM PDT 24	Jul 02 11:27:14 AM PDT 24	3974769455 ps
T746	/workspace/coverage/default/99.chip_sw_all_escalation_resets.1706705503			Jul 02 11:36:50 AM PDT 24	Jul 02 11:46:07 AM PDT 24	5785140090 ps
T178	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2766766627			Jul 02 11:21:38 AM PDT 24	Jul 02 11:36:42 AM PDT 24	12261758512 ps
T730	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1443957961			Jul 02 11:11:22 AM PDT 24	Jul 02 11:20:09 AM PDT 24	3950980200 ps
T943	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2349829816			Jul 02 11:15:21 AM PDT 24	Jul 02 11:33:38 AM PDT 24	6058311836 ps
T185	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1467847625			Jul 02 11:01:36 AM PDT 24	Jul 02 11:05:33 AM PDT 24	3203047060 ps
T143	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3965605036			Jul 02 11:00:18 AM PDT 24	Jul 02 12:03:47 PM PDT 24	24891817473 ps
T392	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1790052953			Jul 02 11:32:50 AM PDT 24	Jul 02 11:45:21 AM PDT 24	5646806252 ps
T144	/workspace/coverage/default/0.chip_sw_otbn_smoketest.1827140845			Jul 02 11:02:04 AM PDT 24	Jul 02 11:20:48 AM PDT 24	6044985804 ps
T393	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2525873628			Jul 02 11:10:11 AM PDT 24	Jul 02 11:23:43 AM PDT 24	8846320940 ps
T394	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2853103930			Jul 02 11:28:59 AM PDT 24	Jul 02 12:29:48 PM PDT 24	14850563396 ps
T179	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.582425813			Jul 02 11:16:20 AM PDT 24	Jul 02 11:19:04 AM PDT 24	3145980471 ps
T395	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2774338184			Jul 02 11:32:59 AM PDT 24	Jul 02 11:39:50 AM PDT 24	3748411760 ps
T141	/workspace/coverage/default/0.chip_sw_power_sleep_load.302727425			Jul 02 11:01:43 AM PDT 24	Jul 02 11:13:59 AM PDT 24	11516738160 ps
T113	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1407157165			Jul 02 11:02:10 AM PDT 24	Jul 02 11:13:52 AM PDT 24	4002951518 ps
T226	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2860868642			Jul 02 11:22:54 AM PDT 24	Jul 02 11:50:43 AM PDT 24	24283784291 ps
T339	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.977565401			Jul 02 11:06:41 AM PDT 24	Jul 02 11:11:47 AM PDT 24	3358690912 ps
T799	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2819560654			Jul 02 11:27:31 AM PDT 24	Jul 02 11:33:55 AM PDT 24	3567085702 ps
T944	/workspace/coverage/default/1.chip_sw_hmac_smoketest.1410229776			Jul 02 11:14:26 AM PDT 24	Jul 02 11:20:25 AM PDT 24	3443807754 ps
T945	/workspace/coverage/default/1.chip_sw_kmac_smoketest.2873123317			Jul 02 11:13:37 AM PDT 24	Jul 02 11:18:45 AM PDT 24	2848760056 ps
T36	/workspace/coverage/default/2.chip_sw_gpio_smoketest.217575456			Jul 02 11:24:08 AM PDT 24	Jul 02 11:28:27 AM PDT 24	3218419055 ps
T946	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.4419215			Jul 02 11:24:43 AM PDT 24	Jul 02 11:28:29 AM PDT 24	3006104674 ps
T252	/workspace/coverage/default/2.chip_sw_rv_timer_irq.2500930751			Jul 02 11:18:29 AM PDT 24	Jul 02 11:24:55 AM PDT 24	3203540870 ps
T786	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3729558805			Jul 02 11:35:13 AM PDT 24	Jul 02 11:43:29 AM PDT 24	3866576174 ps
T947	/workspace/coverage/default/0.chip_sw_example_rom.1908845972			Jul 02 10:56:34 AM PDT 24	Jul 02 10:58:22 AM PDT 24	2651008532 ps
T312	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1470471539			Jul 02 11:06:42 AM PDT 24	Jul 02 11:47:23 AM PDT 24	23029651098 ps
T948	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3230261751			Jul 02 11:19:09 AM PDT 24	Jul 02 11:27:02 AM PDT 24	7575518604 ps
T215	/workspace/coverage/default/61.chip_sw_all_escalation_resets.776085767			Jul 02 11:34:22 AM PDT 24	Jul 02 11:42:47 AM PDT 24	5454828980 ps
T244	/workspace/coverage/default/6.chip_sw_all_escalation_resets.1927746459			Jul 02 11:32:04 AM PDT 24	Jul 02 11:44:35 AM PDT 24	5595199726 ps
T283	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1059756881			Jul 02 11:08:43 AM PDT 24	Jul 02 11:57:35 AM PDT 24	11674789220 ps
T284	/workspace/coverage/default/0.chip_sw_hmac_smoketest.1795171645			Jul 02 11:04:37 AM PDT 24	Jul 02 11:12:24 AM PDT 24	2959584544 ps
T26	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1789207964			Jul 02 10:59:21 AM PDT 24	Jul 02 11:08:17 AM PDT 24	6344509147 ps
T71	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1656290779			Jul 02 11:12:36 AM PDT 24	Jul 02 11:22:18 AM PDT 24	5770472805 ps
T160	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.871973398			Jul 02 11:06:38 AM PDT 24	Jul 02 11:08:35 AM PDT 24	1919584723 ps
T260	/workspace/coverage/default/22.chip_sw_all_escalation_resets.819606660			Jul 02 11:30:34 AM PDT 24	Jul 02 11:44:50 AM PDT 24	5731456740 ps
T285	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2140345932			Jul 02 11:21:18 AM PDT 24	Jul 02 11:29:22 AM PDT 24	3590696872 ps
T279	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1471404810			Jul 02 11:06:09 AM PDT 24	Jul 02 11:21:31 AM PDT 24	6428591996 ps
T142	/workspace/coverage/default/1.chip_sw_power_sleep_load.1221052			Jul 02 11:13:22 AM PDT 24	Jul 02 11:27:05 AM PDT 24	9925898556 ps
T152	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2179893312			Jul 02 11:18:18 AM PDT 24	Jul 02 03:08:40 PM PDT 24	254549217000 ps
T149	/workspace/coverage/default/2.chip_plic_all_irqs_10.695657672			Jul 02 11:20:21 AM PDT 24	Jul 02 11:29:58 AM PDT 24	3627517932 ps
T280	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3759566801			Jul 02 11:00:53 AM PDT 24	Jul 02 11:11:17 AM PDT 24	4919684893 ps
T949	/workspace/coverage/default/70.chip_sw_all_escalation_resets.2821278997			Jul 02 11:34:12 AM PDT 24	Jul 02 11:42:21 AM PDT 24	5264057972 ps
T531	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2484463856			Jul 02 11:01:02 AM PDT 24	Jul 02 11:15:22 AM PDT 24	5326824400 ps
T784	/workspace/coverage/default/81.chip_sw_all_escalation_resets.2262260102			Jul 02 11:37:20 AM PDT 24	Jul 02 11:45:33 AM PDT 24	4473699572 ps
T217	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.209974943			Jul 02 11:01:01 AM PDT 24	Jul 02 11:07:58 AM PDT 24	5285437815 ps
T269	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2350775310			Jul 02 11:05:47 AM PDT 24	Jul 02 12:03:55 PM PDT 24	14719688760 ps
T950	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2732326587			Jul 02 10:58:23 AM PDT 24	Jul 02 12:06:34 PM PDT 24	17116105872 ps
T951	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3508973468			Jul 02 11:28:15 AM PDT 24	Jul 02 11:38:03 AM PDT 24	4359117928 ps
T170	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2844798114			Jul 02 10:58:47 AM PDT 24	Jul 02 11:01:00 AM PDT 24	3245175220 ps
T745	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3641051009			Jul 02 11:15:37 AM PDT 24	Jul 02 11:26:38 AM PDT 24	5997642280 ps
T744	/workspace/coverage/default/49.chip_sw_all_escalation_resets.842183054			Jul 02 11:32:51 AM PDT 24	Jul 02 11:41:42 AM PDT 24	5052168654 ps
T253	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4247904169			Jul 02 11:25:18 AM PDT 24	Jul 02 11:29:29 AM PDT 24	2799733688 ps
T751	/workspace/coverage/default/58.chip_sw_all_escalation_resets.3064167302			Jul 02 11:33:02 AM PDT 24	Jul 02 11:43:37 AM PDT 24	5765570696 ps
T188	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.154129962			Jul 02 11:03:59 AM PDT 24	Jul 02 12:29:26 PM PDT 24	44195452376 ps
T952	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3450700147			Jul 02 10:59:33 AM PDT 24	Jul 02 11:03:48 AM PDT 24	3333293104 ps
T953	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3156357617			Jul 02 11:17:18 AM PDT 24	Jul 02 11:35:17 AM PDT 24	12746059239 ps
T365	/workspace/coverage/default/78.chip_sw_all_escalation_resets.3513918040			Jul 02 11:36:38 AM PDT 24	Jul 02 11:45:38 AM PDT 24	5423901176 ps
T366	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.4039339611			Jul 02 11:07:48 AM PDT 24	Jul 02 12:12:49 PM PDT 24	14860884388 ps
T367	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3509506580			Jul 02 11:25:22 AM PDT 24	Jul 02 11:37:18 AM PDT 24	4616449974 ps
T368	/workspace/coverage/default/46.chip_sw_all_escalation_resets.3806460307			Jul 02 11:32:59 AM PDT 24	Jul 02 11:44:18 AM PDT 24	4879556776 ps
T369	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.989045306			Jul 02 11:17:13 AM PDT 24	Jul 02 11:25:36 AM PDT 24	5295340670 ps
T115	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1683561275			Jul 02 10:59:36 AM PDT 24	Jul 02 11:31:33 AM PDT 24	6974059880 ps
T370	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1591430394			Jul 02 10:58:14 AM PDT 24	Jul 02 11:30:48 AM PDT 24	23447249561 ps
T354	/workspace/coverage/default/39.chip_sw_all_escalation_resets.753233982			Jul 02 11:32:25 AM PDT 24	Jul 02 11:40:21 AM PDT 24	4803054400 ps