dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T435 1 T544 1 T537 1
small_delay 941 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T435 1 T544 1 T537 1
small_delay 641 1 T78 1 T82 1 T450 1
zero 659 1 T79 1 T80 1 T83 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%