Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	519	1			T79	2		T532	1		T536	3
all_values[1]	490	1			T79	1		T532	2		T756	1
all_values[2]	494	1			T78	2		T79	4		T536	1
all_values[3]	523	1			T78	1		T79	4		T539	1
all_values[4]	473	1			T79	3		T756	2		T889	1
all_values[5]	505	1			T78	3		T79	1		T532	2
all_values[6]	511	1			T79	2		T532	3		T536	2
all_values[7]	501	1			T78	1		T79	4		T532	1
all_values[8]	529	1			T78	1		T79	1		T532	3
all_values[9]	509	1			T78	3		T79	4		T536	1
all_values[10]	493	1			T78	1		T756	1		T539	1
all_values[11]	498	1			T79	1		T535	1		T536	1
all_values[12]	517	1			T78	1		T79	2		T532	1
all_values[13]	478	1			T78	1		T79	4		T532	1
all_values[14]	500	1			T79	2		T532	2		T889	1
all_values[15]	527	1			T78	1		T79	1		T535	1
all_values[16]	488	1			T78	2		T79	3		T532	2
all_values[17]	481	1			T532	1		T536	3		T547	2
all_values[18]	508	1			T78	1		T532	1		T756	1
all_values[19]	472	1			T78	2		T79	2		T536	1
all_values[20]	472	1			T78	1		T79	1		T532	1
all_values[21]	471	1			T78	2		T79	3		T547	1
all_values[22]	478	1			T79	2		T532	2		T535	1
all_values[23]	520	1			T78	1		T79	6		T532	1
all_values[24]	478	1			T79	1		T532	2		T539	1
all_values[25]	523	1			T79	1		T532	1		T889	1
all_values[26]	510	1			T78	1		T79	4		T756	1
all_values[27]	499	1			T79	3		T532	1		T554	1
all_values[28]	468	1			T79	3		T532	1		T547	1
all_values[29]	523	1			T78	1		T79	1		T532	1
all_values[30]	465	1			T79	4		T532	1		T547	1
all_values[31]	450	1			T78	1		T756	1		T536	1
all_values[32]	499	1			T79	3		T532	2		T536	1
all_values[33]	483	1			T78	1		T554	2		T629	1
all_values[34]	470	1			T79	1		T532	2		T539	2
all_values[35]	505	1			T78	1		T79	3		T532	1
all_values[36]	508	1			T78	2		T79	2		T247	1
all_values[37]	503	1			T78	1		T79	3		T532	1
all_values[38]	491	1			T79	2		T629	1		T436	1
all_values[39]	477	1			T78	1		T79	2		T532	2
all_values[40]	492	1			T78	2		T79	3		T532	3
all_values[41]	485	1			T532	1		T889	1		T629	2
all_values[42]	526	1			T78	2		T79	2		T889	1
all_values[43]	463	1			T78	1		T79	1		T889	1
all_values[44]	512	1			T79	1		T539	2		T629	1
all_values[45]	505	1			T79	3		T536	2		T539	1
all_values[46]	455	1			T79	1		T756	1		T701	1
all_values[47]	505	1			T79	2		T532	4		T629	3
all_values[48]	464	1			T532	4		T535	1		T629	2
all_values[49]	496	1			T78	1		T79	5		T536	1