Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3725	1			T78	8		T79	11		T532	12
all_values[1]	3759	1			T78	8		T79	8		T532	11
all_values[2]	3711	1			T78	8		T79	11		T532	20
all_values[3]	3836	1			T78	10		T79	11		T532	13
all_values[4]	3730	1			T78	9		T79	10		T532	19
all_values[5]	3754	1			T78	5		T79	12		T532	12
all_values[6]	3714	1			T78	5		T79	14		T532	12
all_values[7]	3694	1			T78	5		T79	8		T532	15
all_values[8]	3703	1			T78	8		T79	13		T532	12
all_values[9]	3715	1			T78	10		T79	12		T532	17
all_values[10]	3750	1			T78	6		T79	5		T532	17
all_values[11]	3663	1			T78	5		T79	10		T532	20
all_values[12]	3778	1			T78	5		T79	9		T532	22
all_values[13]	3737	1			T78	7		T79	14		T532	21
all_values[14]	3835	1			T78	11		T79	11		T532	20
all_values[15]	3728	1			T78	9		T79	17		T532	19
all_values[16]	3766	1			T78	10		T79	10		T532	13
all_values[17]	3831	1			T78	7		T79	18		T532	16
all_values[18]	3815	1			T78	6		T79	12		T532	14
all_values[19]	3868	1			T78	8		T79	10		T532	19
all_values[20]	3737	1			T78	3		T79	11		T532	14
all_values[21]	3829	1			T78	8		T79	16		T532	23
all_values[22]	3658	1			T78	7		T79	6		T532	14
all_values[23]	3650	1			T78	6		T79	12		T532	14
all_values[24]	3743	1			T78	5		T79	12		T532	13
all_values[25]	3677	1			T78	8		T79	10		T532	16
all_values[26]	3742	1			T78	6		T79	10		T532	18
all_values[27]	3838	1			T78	5		T79	14		T532	11
all_values[28]	3794	1			T78	9		T79	12		T532	14
all_values[29]	3659	1			T78	9		T79	9		T532	14
all_values[30]	3781	1			T78	6		T79	6		T532	21
all_values[31]	3701	1			T78	7		T79	15		T532	14
all_values[32]	3762	1			T78	8		T79	15		T532	12
all_values[33]	3787	1			T78	5		T79	15		T532	19
all_values[34]	3777	1			T78	6		T79	10		T532	20
all_values[35]	3774	1			T78	3		T79	5		T532	13
all_values[36]	3612	1			T78	9		T79	15		T532	11
all_values[37]	3743	1			T78	10		T79	19		T532	15
all_values[38]	3862	1			T78	2		T79	8		T532	14
all_values[39]	3823	1			T78	6		T79	20		T532	12
all_values[40]	3762	1			T78	6		T79	10		T532	20
all_values[41]	3777	1			T78	11		T79	17		T532	11
all_values[42]	3798	1			T78	8		T79	14		T532	21
all_values[43]	3803	1			T78	5		T79	11		T532	10
all_values[44]	3693	1			T78	3		T79	13		T532	12
all_values[45]	3779	1			T78	7		T79	8		T532	18
all_values[46]	3727	1			T78	5		T79	16		T532	13
all_values[47]	3695	1			T78	6		T79	9		T532	17
all_values[48]	3685	1			T78	5		T79	11		T532	17
all_values[49]	3835	1			T78	6		T79	14		T532	16
all_values[50]	3779	1			T78	8		T79	9		T532	19
all_values[51]	3854	1			T78	7		T79	13		T532	18
all_values[52]	3722	1			T78	15		T79	10		T532	17
all_values[53]	3781	1			T78	3		T79	8		T532	16
all_values[54]	3706	1			T78	6		T79	14		T532	20
all_values[55]	3813	1			T78	14		T79	11		T532	19
all_values[56]	3681	1			T78	4		T79	12		T532	19
all_values[57]	3799	1			T78	1		T79	13		T532	16
all_values[58]	3795	1			T78	8		T79	17		T532	23
all_values[59]	3665	1			T78	7		T79	7		T532	14
all_values[60]	3719	1			T78	1		T79	17		T532	10
all_values[61]	3747	1			T78	7		T79	13		T532	12
all_values[62]	3786	1			T78	12		T79	9		T532	26
all_values[63]	3792	1			T78	7		T79	11		T532	12