Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3736998	1			T88	2005		T89	1590		T91	1379
values[2]	761406	1			T88	161		T91	399		T249	19
values[3]	106257	1			T88	4		T91	8		T249	14
values[4]	55941	1			T249	2		T500	100		T507	3
values[5]	37185	1			T500	79		T507	1		T426	62
values[6]	27132	1			T500	100		T426	70		T501	40
values[7]	22049	1			T500	117		T426	82		T501	24
values[8]	18939	1			T500	96		T426	62		T501	28
values[9]	16906	1			T500	116		T426	76		T501	30
values[10]	15149	1			T500	128		T426	73		T501	27
values[11]	13800	1			T500	126		T426	88		T501	41
values[12]	13527	1			T500	103		T426	69		T501	29
values[13]	13213	1			T500	101		T426	82		T501	24
values[14]	12453	1			T500	96		T426	67		T501	17
values[15]	11560	1			T500	90		T426	85		T501	24
values[16]	11474	1			T500	81		T426	86		T501	16
values[17]	10832	1			T500	87		T426	89		T501	16
values[18]	10607	1			T500	86		T426	84		T501	21
values[19]	10068	1			T500	113		T426	50		T501	26
values[20]	9602	1			T500	117		T426	54		T501	12
values[21]	9208	1			T500	113		T426	74		T501	11
values[22]	9161	1			T500	81		T426	69		T501	16
values[23]	8955	1			T500	77		T426	73		T501	13
values[24]	8676	1			T500	98		T426	87		T501	11
values[25]	8519	1			T500	92		T426	58		T501	8
values[26]	8037	1			T500	78		T426	51		T501	8
values[27]	7669	1			T500	72		T426	55		T501	10
values[28]	7222	1			T500	79		T426	73		T501	15
values[29]	6758	1			T500	85		T426	34		T501	13
values[30]	6165	1			T500	77		T426	49		T501	11
values[31]	5801	1			T500	52		T426	46		T501	5
values[32]	5453	1			T500	33		T426	43		T501	3
values[33]	5125	1			T500	23		T426	31		T501	3
values[34]	4632	1			T500	22		T426	37		T501	3
values[35]	4520	1			T500	21		T426	27		T501	3
values[36]	4110	1			T500	19		T426	18		T501	2
values[37]	3963	1			T500	14		T426	19		T501	4
values[38]	3673	1			T500	21		T426	15		T501	4
values[39]	3448	1			T500	13		T426	8		T501	2
values[40]	3356	1			T500	10		T426	13		T501	2
values[41]	3347	1			T500	17		T426	6		T501	4
values[42]	3187	1			T500	15		T426	2		T501	3
values[43]	3169	1			T500	7		T426	4		T501	4
values[44]	3053	1			T500	17		T426	6		T501	3
values[45]	2919	1			T500	11		T426	3		T501	4
values[46]	2984	1			T500	10		T426	4		T501	4
values[47]	2949	1			T500	5		T426	6		T501	5
values[48]	2881	1			T500	5		T426	1		T501	15
values[49]	2741	1			T500	7		T426	1		T501	8
values[50]	2799	1			T500	15		T501	2		T505	10
values[51]	2684	1			T500	9		T501	2		T505	7
values[52]	2592	1			T500	7		T501	2		T505	6
values[53]	2597	1			T500	8		T501	7		T505	3
values[54]	2507	1			T500	7		T501	7		T505	5
values[55]	2414	1			T500	13		T501	9		T505	2
values[56]	2426	1			T500	8		T501	4		T505	2
values[57]	2378	1			T500	3		T501	5		T505	1
values[58]	2289	1			T500	11		T501	1		T505	2
values[59]	2359	1			T500	6		T501	4		T505	1
values[60]	2391	1			T500	6		T501	2		T505	2
values[61]	2602	1			T500	3		T501	1		T505	2
values[62]	3617	1			T500	4		T501	1		T505	2
values[63]	9683	1			T500	8		T501	14		T505	3
values[64]	229020	1			T500	82		T501	53		T505	118

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4763961	1			T88	2141		T89	1592		T91	1277
values[2]	812666	1			T88	140		T91	330		T249	28
values[3]	85943	1			T88	6		T91	61		T249	10
values[4]	15458	1			T91	3		T249	1		T250	12
values[5]	6243	1			T500	1		T507	1		T508	6
values[6]	3865	1			T500	1		T508	2		T501	11
values[7]	3036	1			T500	7		T508	2		T501	12
values[8]	2583	1			T500	5		T501	3		T505	4
values[9]	2150	1			T500	1		T501	2		T505	4
values[10]	1940	1			T500	1		T501	4		T505	4
values[11]	1867	1			T500	1		T501	9		T505	4
values[12]	1635	1			T500	1		T501	14		T505	2
values[13]	1409	1			T500	1		T501	14		T505	2
values[14]	1391	1			T500	5		T501	18		T505	2
values[15]	1284	1			T500	5		T501	30		T505	2
values[16]	1086	1			T500	1		T501	16		T505	2
values[17]	969	1			T500	3		T501	12		T505	2
values[18]	951	1			T500	3		T501	3		T505	2
values[19]	924	1			T500	2		T501	1		T505	2
values[20]	874	1			T500	1		T505	2		T392	1
values[21]	813	1			T500	1		T505	2		T392	1
values[22]	761	1			T500	1		T505	9		T392	1
values[23]	787	1			T500	2		T505	1		T392	1
values[24]	690	1			T500	1		T505	2		T392	1
values[25]	628	1			T500	1		T505	1		T392	1
values[26]	673	1			T500	1		T505	2		T392	1
values[27]	649	1			T500	2		T505	3		T392	1
values[28]	613	1			T500	1		T505	6		T392	1
values[29]	600	1			T500	3		T505	10		T392	1
values[30]	534	1			T500	1		T505	3		T392	1
values[31]	499	1			T500	1		T505	1		T392	1
values[32]	487	1			T500	1		T505	1		T392	1
values[33]	438	1			T500	2		T505	1		T392	1
values[34]	449	1			T500	2		T505	2		T392	1
values[35]	466	1			T500	1		T505	3		T392	1
values[36]	429	1			T500	2		T505	3		T392	1
values[37]	421	1			T500	1		T505	3		T392	1
values[38]	385	1			T500	2		T505	1		T392	1
values[39]	418	1			T500	2		T505	2		T392	1
values[40]	394	1			T500	2		T505	2		T392	1
values[41]	410	1			T500	4		T505	1		T392	1
values[42]	415	1			T500	4		T505	1		T392	1
values[43]	377	1			T500	2		T505	1		T392	1
values[44]	377	1			T500	1		T505	2		T392	1
values[45]	356	1			T500	1		T505	1		T392	1
values[46]	347	1			T500	1		T505	1		T392	1
values[47]	354	1			T500	1		T505	1		T392	1
values[48]	342	1			T500	3		T505	2		T392	1
values[49]	339	1			T500	1		T505	1		T392	1
values[50]	342	1			T500	1		T505	2		T392	1
values[51]	336	1			T500	2		T505	1		T392	1
values[52]	353	1			T500	2		T505	2		T392	1
values[53]	305	1			T500	1		T505	3		T392	1
values[54]	308	1			T500	2		T505	6		T392	1
values[55]	330	1			T500	3		T505	2		T392	1
values[56]	305	1			T500	2		T505	2		T392	1
values[57]	296	1			T500	2		T505	1		T392	1
values[58]	295	1			T500	1		T505	1		T392	1
values[59]	288	1			T500	1		T505	1		T392	1
values[60]	296	1			T500	2		T505	1		T392	1
values[61]	293	1			T500	1		T505	1		T392	1
values[62]	474	1			T500	1		T505	1		T392	1
values[63]	1758	1			T500	4		T505	3		T392	1
values[64]	23533	1			T500	179		T505	129		T392	148

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	583464	1			T88	254		T89	1633		T91	15
values[2]	2655672	1			T88	1700		T91	1153		T249	129
values[3]	1190748	1			T88	263		T91	395		T249	59
values[4]	146116	1			T88	4		T91	9		T249	5
values[5]	75723	1			T249	1		T250	1		T500	108
values[6]	48790	1			T500	120		T426	105		T477	2
values[7]	35531	1			T500	89		T426	82		T477	3
values[8]	28255	1			T500	81		T426	65		T477	6
values[9]	23867	1			T500	95		T426	76		T501	68
values[10]	20989	1			T500	102		T426	67		T501	78
values[11]	18901	1			T500	99		T426	68		T501	98
values[12]	17591	1			T500	105		T426	71		T501	71
values[13]	16339	1			T500	93		T426	83		T501	74
values[14]	14725	1			T500	75		T426	65		T501	106
values[15]	14267	1			T500	88		T426	70		T501	95
values[16]	13484	1			T500	102		T426	55		T501	87
values[17]	12700	1			T500	97		T426	71		T501	64
values[18]	12164	1			T500	100		T426	110		T501	96
values[19]	11958	1			T500	102		T426	87		T501	96
values[20]	11672	1			T500	127		T426	84		T501	75
values[21]	11174	1			T500	116		T426	99		T501	52
values[22]	10604	1			T500	87		T426	83		T501	33
values[23]	9883	1			T500	89		T426	86		T501	20
values[24]	9802	1			T500	108		T426	67		T501	14
values[25]	9556	1			T500	104		T426	57		T501	13
values[26]	8986	1			T500	94		T426	73		T501	30
values[27]	8581	1			T500	92		T426	78		T501	12
values[28]	7935	1			T500	89		T426	71		T501	13
values[29]	7326	1			T500	58		T426	55		T501	9
values[30]	6891	1			T500	68		T426	52		T501	8
values[31]	6593	1			T500	88		T426	51		T501	13
values[32]	6095	1			T500	68		T426	22		T501	6
values[33]	5507	1			T500	50		T426	26		T501	7
values[34]	5296	1			T500	27		T426	24		T501	7
values[35]	4741	1			T500	14		T426	20		T501	6
values[36]	4464	1			T500	13		T426	17		T501	10
values[37]	4174	1			T500	13		T426	22		T501	7
values[38]	3960	1			T500	14		T426	15		T501	4
values[39]	3894	1			T500	7		T426	15		T501	8
values[40]	3813	1			T500	9		T426	17		T501	16
values[41]	3643	1			T500	18		T426	8		T501	11
values[42]	3537	1			T500	22		T426	10		T501	17
values[43]	3467	1			T500	12		T426	8		T501	12
values[44]	3423	1			T500	6		T426	8		T501	9
values[45]	3208	1			T500	9		T426	12		T501	4
values[46]	3249	1			T500	16		T426	8		T501	4
values[47]	3268	1			T500	14		T426	4		T501	13
values[48]	3238	1			T500	15		T426	9		T501	20
values[49]	3170	1			T500	16		T426	11		T501	14
values[50]	3003	1			T500	11		T426	7		T501	10
values[51]	2911	1			T500	9		T426	21		T501	13
values[52]	2835	1			T500	14		T426	18		T501	6
values[53]	2749	1			T500	9		T426	13		T501	7
values[54]	2829	1			T500	11		T426	10		T501	7
values[55]	2809	1			T500	24		T426	11		T501	2
values[56]	2791	1			T500	9		T426	5		T501	1
values[57]	2693	1			T500	16		T426	8		T501	1
values[58]	2598	1			T500	12		T426	2		T501	2
values[59]	2494	1			T500	2		T501	3		T421	13
values[60]	2523	1			T500	1		T501	4		T421	13
values[61]	2583	1			T500	1		T501	9		T421	13
values[62]	3414	1			T500	1		T501	2		T421	13
values[63]	7991	1			T500	2		T501	8		T421	13
values[64]	221435	1			T500	76		T501	69		T421	2309