Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1936062	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37493800

1

T5

17733

T6

4489

T17

6842

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27452603	1			T5	13493		T6	1572		T17	3060
values[0x0]	10552819	1			T5	4240		T6	2917		T17	3782
values[0x1]	1424440	1			T5	3802		T6	261		T17	350

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	644073	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38785789

1

T5

21535

T6

4750

T17

7192

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18556906	1			T5	10768		T6	2375		T17	3596
valid_sources[0x01]	18552054	1			T5	10767		T6	2375		T17	3596
valid_sources[0x02]	37291	1			T171	1		T172	1		T87	220
valid_sources[0x03]	37152	1			T92	1		T172	2		T87	97
valid_sources[0x04]	36834	1			T80	10		T92	1		T172	2
valid_sources[0x05]	36573	1			T90	4		T171	3		T87	175
valid_sources[0x06]	37346	1			T92	2		T87	205		T135	438
valid_sources[0x07]	37383	1			T90	1		T87	208		T135	394
valid_sources[0x08]	37352	1			T92	1		T87	174		T135	380
valid_sources[0x09]	37753	1			T87	187		T135	422		T506	23
valid_sources[0x0a]	37003	1			T171	1		T92	1		T87	145
valid_sources[0x0b]	36912	1			T87	143		T135	326		T506	32
valid_sources[0x0c]	37991	1			T171	3		T87	208		T135	460
valid_sources[0x0d]	37026	1			T65	5		T171	1		T92	1
valid_sources[0x0e]	37669	1			T171	4		T87	167		T135	361
valid_sources[0x0f]	37063	1			T171	1		T92	1		T172	4
valid_sources[0x10]	37701	1			T90	3		T87	147		T135	363
valid_sources[0x11]	37296	1			T171	4		T87	197		T135	342
valid_sources[0x12]	37520	1			T90	2		T87	124		T135	407
valid_sources[0x13]	37699	1			T171	1		T172	6		T87	217
valid_sources[0x14]	37325	1			T65	13		T92	1		T87	159
valid_sources[0x15]	38423	1			T172	6		T87	173		T135	373
valid_sources[0x16]	38183	1			T172	1		T87	153		T135	353
valid_sources[0x17]	36980	1			T171	1		T92	1		T87	156
valid_sources[0x18]	37419	1			T90	6		T87	159		T135	366
valid_sources[0x19]	37796	1			T90	5		T171	3		T87	229
valid_sources[0x1a]	37190	1			T171	2		T92	1		T87	166
valid_sources[0x1b]	37341	1			T171	1		T92	1		T172	1
valid_sources[0x1c]	37043	1			T90	3		T87	143		T135	454
valid_sources[0x1d]	36950	1			T171	2		T172	1		T87	119
valid_sources[0x1e]	37336	1			T171	1		T92	2		T172	3
valid_sources[0x1f]	37020	1			T65	9		T87	142		T135	366
valid_sources[0x20]	37734	1			T90	4		T87	131		T135	424

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26741132

1

T5

13493

T6

1572

T17

3060

values[0x0]

all_enables

biggest_size

10506876

1

T5

4240

T6

2917

T17

3782

values[0x1]

all_enables

biggest_size

245792

1

T80

16

T90

17

T65

23

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2938479	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

465360

1

T88

13

T89

199

T91

252

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1154573	1			T88	46		T89	545		T91	596
values[0x0]	1099122	1			T88	9		T89	539		T91	605
values[0x1]	1150144	1			T88	46		T89	506		T91	585

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2276663	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1127176

1

T88

42

T89

501

T91

579

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53275	1			T89	25		T91	15		T249	3
valid_sources[0x01]	52630	1			T89	55		T91	22		T250	2
valid_sources[0x02]	52245	1			T88	1		T91	13		T500	62
valid_sources[0x03]	52846	1			T88	1		T89	29		T91	22
valid_sources[0x04]	52392	1			T88	4		T89	52		T91	16
valid_sources[0x05]	52701	1			T88	3		T89	8		T91	18
valid_sources[0x06]	53119	1			T88	3		T89	15		T91	32
valid_sources[0x07]	53411	1			T88	1		T91	41		T250	2
valid_sources[0x08]	53559	1			T88	3		T89	15		T91	25
valid_sources[0x09]	52842	1			T88	4		T89	31		T91	10
valid_sources[0x0a]	53776	1			T88	2		T89	49		T91	23
valid_sources[0x0b]	52326	1			T89	34		T91	26		T250	3
valid_sources[0x0c]	53543	1			T89	57		T91	41		T250	1
valid_sources[0x0d]	52774	1			T88	3		T89	63		T91	13
valid_sources[0x0e]	52819	1			T89	5		T91	52		T250	1
valid_sources[0x0f]	52874	1			T89	14		T91	11		T249	5
valid_sources[0x10]	52836	1			T88	1		T91	15		T427	17
valid_sources[0x11]	52815	1			T88	4		T89	39		T91	34
valid_sources[0x12]	52817	1			T88	1		T89	13		T91	39
valid_sources[0x13]	54214	1			T88	1		T89	24		T91	65
valid_sources[0x14]	52815	1			T89	30		T91	30		T500	69
valid_sources[0x15]	53261	1			T88	5		T89	13		T91	14
valid_sources[0x16]	53577	1			T88	2		T89	74		T91	29
valid_sources[0x17]	53233	1			T88	3		T89	17		T91	23
valid_sources[0x18]	52055	1			T88	2		T91	17		T427	6
valid_sources[0x19]	53804	1			T88	1		T89	24		T91	48
valid_sources[0x1a]	53228	1			T88	4		T91	76		T250	4
valid_sources[0x1b]	54166	1			T88	1		T89	5		T91	21
valid_sources[0x1c]	52633	1			T89	21		T91	59		T250	2
valid_sources[0x1d]	53145	1			T89	30		T91	55		T500	71
valid_sources[0x1e]	52609	1			T89	26		T91	33		T249	3
valid_sources[0x1f]	52846	1			T88	2		T89	83		T91	43
valid_sources[0x20]	54418	1			T88	2		T91	38		T250	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49057

1

T88

6

T89

26

T91

25

values[0x0]

all_enables

biggest_size

367695

1

T88

4

T89

156

T91

203

values[0x1]

all_enables

biggest_size

48608

1

T88

3

T89

17

T91

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3138921	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

511347

1

T88

7

T89

226

T91

240

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1248610	1			T88	48		T89	527		T91	557
values[0x0]	1153377	1			T88	3		T89	523		T91	550
values[0x1]	1248281	1			T88	50		T89	542		T91	564

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2408682	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1241586

1

T88

40

T89

537

T91

578

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57242	1			T88	1		T89	23		T91	10
valid_sources[0x01]	57703	1			T88	1		T89	50		T91	45
valid_sources[0x02]	57759	1			T88	2		T91	12		T250	2
valid_sources[0x03]	57474	1			T88	2		T89	26		T91	28
valid_sources[0x04]	57856	1			T88	1		T89	33		T91	52
valid_sources[0x05]	57320	1			T89	5		T91	64		T249	1
valid_sources[0x06]	56769	1			T88	2		T89	21		T91	33
valid_sources[0x07]	56506	1			T88	1		T91	21		T250	3
valid_sources[0x08]	56535	1			T88	5		T89	29		T91	24
valid_sources[0x09]	55899	1			T88	3		T89	40		T91	17
valid_sources[0x0a]	56368	1			T88	1		T89	38		T91	56
valid_sources[0x0b]	56650	1			T89	34		T91	24		T500	78
valid_sources[0x0c]	57757	1			T88	2		T89	23		T91	23
valid_sources[0x0d]	56654	1			T88	2		T89	63		T91	44
valid_sources[0x0e]	56553	1			T88	4		T89	10		T91	29
valid_sources[0x0f]	57462	1			T88	2		T89	17		T91	6
valid_sources[0x10]	56426	1			T91	32		T249	4		T427	10
valid_sources[0x11]	57510	1			T88	3		T89	17		T91	11
valid_sources[0x12]	56617	1			T88	2		T89	25		T91	9
valid_sources[0x13]	56867	1			T88	1		T89	28		T91	36
valid_sources[0x14]	56431	1			T88	1		T89	26		T91	70
valid_sources[0x15]	57155	1			T88	4		T89	8		T91	38
valid_sources[0x16]	58114	1			T89	74		T91	7		T249	4
valid_sources[0x17]	56855	1			T88	2		T89	8		T91	43
valid_sources[0x18]	57243	1			T88	3		T91	13		T250	1
valid_sources[0x19]	57419	1			T88	2		T89	28		T91	20
valid_sources[0x1a]	57581	1			T91	18		T249	1		T427	5
valid_sources[0x1b]	56349	1			T88	1		T89	10		T91	17
valid_sources[0x1c]	56756	1			T89	17		T91	19		T249	2
valid_sources[0x1d]	56289	1			T89	37		T91	37		T249	8
valid_sources[0x1e]	57517	1			T88	1		T89	38		T91	66
valid_sources[0x1f]	56785	1			T89	91		T91	12		T250	2
valid_sources[0x20]	58349	1			T88	3		T91	10		T249	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53490

1

T88

2

T89

17

T91

27

values[0x0]

all_enables

biggest_size

404160

1

T89

180

T91

190

T249

14

values[0x1]

all_enables

biggest_size

53697

1

T88

5

T89

29

T91

23

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2969942	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

469317

1

T88

5

T89

237

T91

225

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1163305	1			T88	54		T89	519		T91	523
values[0x0]	1111035	1			T88	8		T89	561		T91	546
values[0x1]	1164919	1			T88	46		T89	553		T91	503

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2299824	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1139435

1

T88

25

T89

528

T91

517

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53061	1			T88	3		T89	28		T91	14
valid_sources[0x01]	55222	1			T88	1		T89	39		T91	27
valid_sources[0x02]	53017	1			T88	1		T91	11		T249	5
valid_sources[0x03]	53123	1			T88	5		T89	25		T91	22
valid_sources[0x04]	53703	1			T88	1		T89	51		T91	29
valid_sources[0x05]	53839	1			T88	2		T89	14		T91	27
valid_sources[0x06]	53823	1			T88	3		T89	23		T91	15
valid_sources[0x07]	53324	1			T88	3		T91	28		T249	1
valid_sources[0x08]	54034	1			T88	2		T89	25		T91	15
valid_sources[0x09]	52109	1			T88	4		T89	28		T91	32
valid_sources[0x0a]	53501	1			T89	52		T91	21		T249	6
valid_sources[0x0b]	54425	1			T88	1		T89	30		T91	15
valid_sources[0x0c]	53300	1			T88	3		T89	76		T91	21
valid_sources[0x0d]	52495	1			T88	4		T89	42		T91	26
valid_sources[0x0e]	52605	1			T88	1		T89	14		T91	26
valid_sources[0x0f]	54367	1			T88	1		T89	13		T91	19
valid_sources[0x10]	53374	1			T91	22		T250	1		T427	10
valid_sources[0x11]	53616	1			T89	27		T91	21		T249	7
valid_sources[0x12]	52775	1			T88	2		T89	33		T91	30
valid_sources[0x13]	53875	1			T88	1		T89	35		T91	22
valid_sources[0x14]	53803	1			T88	2		T89	22		T91	31
valid_sources[0x15]	53282	1			T88	5		T89	16		T91	24
valid_sources[0x16]	53502	1			T89	82		T91	22		T249	1
valid_sources[0x17]	52985	1			T88	1		T89	12		T91	21
valid_sources[0x18]	53413	1			T88	1		T91	25		T249	1
valid_sources[0x19]	53911	1			T88	4		T89	32		T91	16
valid_sources[0x1a]	53254	1			T91	26		T249	3		T250	4
valid_sources[0x1b]	54155	1			T88	1		T89	18		T91	31
valid_sources[0x1c]	53477	1			T89	17		T91	24		T249	3
valid_sources[0x1d]	54441	1			T88	3		T89	30		T91	27
valid_sources[0x1e]	53745	1			T88	1		T89	31		T91	20
valid_sources[0x1f]	54198	1			T88	3		T89	80		T91	36
valid_sources[0x20]	54234	1			T91	35		T250	1		T500	86

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49081

1

T89

21

T91

22

T249

2

values[0x0]

all_enables

biggest_size

371146

1

T88

2

T89

194

T91

172

values[0x1]

all_enables

biggest_size

49090

1

T88

3

T89

22

T91

31