Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : ast
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.16 84.16

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_ast_0.1/rtl/ast.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_ast 93.17 93.17


Module Instance : tb.dut.u_ast

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.17 93.17


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.17 93.17


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.83 80.00 100.00 98.48 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : ast
TotalCoveredPercent
Totals 231 183 79.22
Total Bits 972 818 84.16
Total Bits 0->1 486 412 84.77
Total Bits 1->0 486 406 83.54

Ports 231 183 79.22
Port Bits 972 818 84.16
Port Bits 0->1 486 412 84.77
Port Bits 1->0 486 406 83.54

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
tl_i.d_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_address[9:0] Yes Yes *T87,*T88,*T89 Yes T87,T88,T89 INPUT
tl_i.a_address[18:10] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[21:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T80,T90,T65 Yes T80,T90,T65 INPUT
tl_i.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_o.a_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_o.d_error Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T88,T135,T89 Yes T88,T135,T89 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T45,T46,T47 Yes T5,T6,T17 OUTPUT
tl_o.d_data[31:0] Yes Yes T45,T46,T47 Yes T5,T6,T17 OUTPUT
tl_o.d_sink Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_source[5:0] Yes Yes *T88,*T89,*T91 Yes T88,T89,T91 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T88,*T135,*T89 Yes T88,T135,T89 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
ast_init_done_o[3:0] Yes Yes T5,T6,T17 Yes T45,T46,T47 OUTPUT
clk_ast_adc_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_adc_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
clk_ast_alert_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_alert_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
clk_ast_es_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_es_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
clk_ast_rng_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_rng_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
clk_ast_tlul_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_tlul_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
clk_ast_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_usb_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
clk_ast_ext_i Yes Yes T22,T63,T72 Yes T22,T23,T63 INPUT
por_ni Yes Yes T20,T21,T22 Yes T4,T5,T6 INPUT
sns_clks_i.clk_usb_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div2_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div4_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div4_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div4_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div2_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_usb_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div4_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_otbn Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_kmac Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_hmac Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_aes Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div2_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_usb_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div4_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_i2c2_n[0] No No No INPUT
sns_rsts_i.rst_i2c2_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_i2c1_n[0] No No No INPUT
sns_rsts_i.rst_i2c1_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_i2c0_n[0] No No No INPUT
sns_rsts_i.rst_i2c0_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_usb_aon_n[0] No No No INPUT
sns_rsts_i.rst_usb_aon_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_usb_n[0] No No No INPUT
sns_rsts_i.rst_usb_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_spi_host1_n[0] No No No INPUT
sns_rsts_i.rst_spi_host1_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_spi_host0_n[0] No No No INPUT
sns_rsts_i.rst_spi_host0_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_spi_device_n[0] No No No INPUT
sns_rsts_i.rst_spi_device_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_sys_io_div4_n[0] Yes Yes *T45,*T46,*T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_sys_io_div4_n[1] No No No INPUT
sns_rsts_i.rst_sys_n[0] No No No INPUT
sns_rsts_i.rst_sys_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_usb_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_io_div4_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_io_div4_shadowed_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_io_div2_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_io_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_aon_n[0] Yes Yes *T45,*T46,*T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_aon_n[1] No No No INPUT
sns_rsts_i.rst_lc_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_shadowed_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_usb_n[0] Yes Yes *T20,*T21,*T22 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_usb_n[1] No No No INPUT
sns_rsts_i.rst_por_io_div4_n[0] Yes Yes *T20,*T21,*T22 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_io_div4_n[1] No No No INPUT
sns_rsts_i.rst_por_io_div2_n[0] Yes Yes *T20,*T21,*T22 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_io_div2_n[1] No No No INPUT
sns_rsts_i.rst_por_io_n[0] Yes Yes *T20,*T21,*T22 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_io_n[1] No No No INPUT
sns_rsts_i.rst_por_n[0] Yes Yes *T20,*T21,*T22 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_n[1] No No No INPUT
sns_rsts_i.rst_por_aon_n[1:0] Yes Yes T20,T21,T22 Yes T4,T5,T6 INPUT
sns_spi_ext_clk_i Yes Yes T26,T76,T27 Yes T26,T23,T76 INPUT
vcc_supp_i Unreachable Unreachable Unreachable INPUT
vcaon_supp_i Unreachable Unreachable Unreachable INPUT
vcmain_supp_i Unreachable Unreachable Unreachable INPUT
vioa_supp_i Unreachable Unreachable Unreachable INPUT
viob_supp_i Unreachable Unreachable Unreachable INPUT
ast_pwst_o.io_pok[1:0] Yes Yes T149,T150,T151 Yes T4,T5,T6 OUTPUT
ast_pwst_o.main_pok Yes Yes T103,T20,T21 Yes T4,T5,T6 OUTPUT
ast_pwst_o.vcc_pok No No Yes T4,T5,T6 OUTPUT
ast_pwst_o.aon_pok Yes Yes T20,T21,T22 Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.io_pok[1:0] Yes Yes T149,T150,T151 Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.main_pok Yes Yes T103,T20,T21 Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.vcc_pok No No Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.aon_pok Yes Yes T20,T21,T22 Yes T4,T5,T6 OUTPUT
main_pd_ni Yes Yes T103,T132,T31 Yes T103,T132,T31 INPUT
main_env_iso_en_i Yes Yes T4,T5,T6 Yes T103,T20,T21 INPUT
flash_power_down_h_o Yes Yes T4,T5,T6 Yes T103,T132,T31 OUTPUT
flash_power_ready_h_o No No Yes T4,T5,T6 OUTPUT
otp_power_seq_i[1:0] No No No INPUT
otp_power_seq_h_o[0] No No No OUTPUT
otp_power_seq_h_o[1] Yes Yes T4,T5,T6 Yes T103,T132,T31 OUTPUT
clk_src_sys_en_i Yes Yes T19,T70,T71 Yes T4,T5,T6 INPUT
clk_src_sys_jen_i[3:0] Yes Yes T17,T46,T126 Yes T46,T127,T125 INPUT
clk_src_sys_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_sys_val_o Yes Yes T19,T70,T71 Yes T4,T5,T6 OUTPUT
clk_src_aon_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_aon_val_o Yes Yes T128,T129,T130 Yes T4,T5,T6 OUTPUT
clk_src_io_en_i Yes Yes T19,T70,T71 Yes T4,T5,T6 INPUT
clk_src_io_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_io_val_o Yes Yes T19,T70,T71 Yes T4,T5,T6 OUTPUT
clk_src_io_48m_o[3:0] Yes Yes T22,T63,T72 Yes T22,T63,T72 OUTPUT
usb_ref_pulse_i Yes Yes T36,T37,T38 Yes T36,T37,T38 INPUT
usb_ref_val_i Yes Yes T36,T37,T38 Yes T36,T37,T38 INPUT
clk_src_usb_en_i Yes Yes T19,T70,T71 Yes T4,T5,T6 INPUT
clk_src_usb_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_usb_val_o Yes Yes T19,T70,T71 Yes T4,T5,T6 OUTPUT
usb_io_pu_cal_o[19:0] Unreachable Unreachable Unreachable OUTPUT
adc_pd_i Yes Yes T103,T2,T119 Yes T103,T2,T119 INPUT
adc_a0_ai No No Yes T23,T24,T25 INPUT
adc_a1_ai No No Yes T23,T24,T25 INPUT
adc_chnsel_i[1:0] Yes Yes T103,T2,T119 Yes T103,T2,T119 INPUT
adc_d_o[9:0] Yes Yes T103,T2,T120 Yes T103,T2,T120 OUTPUT
adc_d_val_o Yes Yes T103,T2,T119 Yes T103,T2,T119 OUTPUT
rng_en_i Yes Yes T45,T46,T47 Yes T5,T6,T17 INPUT
rng_fips_i Yes Yes T115,T133,T134 Yes T45,T46,T105 INPUT
rng_val_o Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
rng_b_o[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
entropy_rsp_i.edn_bus[31:0] Yes Yes T17,T26,T97 Yes T5,T6,T17 INPUT
entropy_rsp_i.edn_fips Yes Yes T121,T122,T123 Yes T46,T124,T125 INPUT
entropy_rsp_i.edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
entropy_req_o.edn_req Yes Yes T5,T6,T17 Yes T4,T5,T6 OUTPUT
alert_rsp_i.alerts_trig[0].n Yes Yes T2,T136,T137 Yes T2,T136,T137 INPUT
alert_rsp_i.alerts_trig[0].p Yes Yes T2,T136,T137 Yes T2,T136,T137 INPUT
alert_rsp_i.alerts_trig[1].n Yes Yes T136,T138,T139 Yes T136,T138,T139 INPUT
alert_rsp_i.alerts_trig[1].p Yes Yes T136,T138,T139 Yes T136,T138,T139 INPUT
alert_rsp_i.alerts_trig[2].n Yes Yes T136,T137,T141 Yes T136,T137,T141 INPUT
alert_rsp_i.alerts_trig[2].p Yes Yes T136,T137,T141 Yes T136,T137,T141 INPUT
alert_rsp_i.alerts_trig[3].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[3].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[4].n Yes Yes T136,T137,T138 Yes T136,T137,T138 INPUT
alert_rsp_i.alerts_trig[4].p Yes Yes T136,T137,T138 Yes T136,T137,T138 INPUT
alert_rsp_i.alerts_trig[5].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[5].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[6].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[6].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[7].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[7].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[8].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[8].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[9].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[9].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[10].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[10].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[0].n Yes Yes T2,T136,T137 Yes T2,T136,T137 INPUT
alert_rsp_i.alerts_ack[0].p Yes Yes T2,T136,T137 Yes T2,T136,T137 INPUT
alert_rsp_i.alerts_ack[1].n Yes Yes T136,T138,T139 Yes T136,T138,T139 INPUT
alert_rsp_i.alerts_ack[1].p Yes Yes T136,T138,T139 Yes T136,T138,T139 INPUT
alert_rsp_i.alerts_ack[2].n Yes Yes T136,T137,T141 Yes T136,T137,T141 INPUT
alert_rsp_i.alerts_ack[2].p Yes Yes T136,T137,T141 Yes T136,T137,T141 INPUT
alert_rsp_i.alerts_ack[3].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[3].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[4].n Yes Yes T136,T137,T138 Yes T136,T137,T138 INPUT
alert_rsp_i.alerts_ack[4].p Yes Yes T136,T137,T138 Yes T136,T137,T138 INPUT
alert_rsp_i.alerts_ack[5].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[5].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[6].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[6].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[7].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[7].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[8].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[8].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[9].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[9].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[10].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[10].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_req_o.alerts[0].n Yes Yes T2,T136,T137 Yes T2,T137,T14 OUTPUT
alert_req_o.alerts[0].p Yes Yes T2,T137,T14 Yes T2,T136,T137 OUTPUT
alert_req_o.alerts[1].n Yes Yes T136,T138,T139 Yes T138,T139,T140 OUTPUT
alert_req_o.alerts[1].p Yes Yes T138,T139,T140 Yes T136,T138,T139 OUTPUT
alert_req_o.alerts[2].n Yes Yes T136,T137,T141 Yes T137,T141,T142 OUTPUT
alert_req_o.alerts[2].p Yes Yes T137,T141,T142 Yes T136,T137,T141 OUTPUT
alert_req_o.alerts[3].n Yes Yes T136,T143,T144 Yes T145,T146 OUTPUT
alert_req_o.alerts[3].p Yes Yes T145,T146 Yes T136,T143,T144 OUTPUT
alert_req_o.alerts[4].n Yes Yes T136,T137,T138 Yes T137,T138,T139 OUTPUT
alert_req_o.alerts[4].p Yes Yes T137,T138,T139 Yes T136,T137,T138 OUTPUT
alert_req_o.alerts[5].n Yes Yes T136,T143,T144 Yes T142,T145,T146 OUTPUT
alert_req_o.alerts[5].p Yes Yes T142,T145,T146 Yes T136,T143,T144 OUTPUT
alert_req_o.alerts[6].n Yes Yes T136,T143,T144 Yes T142,T145,T147 OUTPUT
alert_req_o.alerts[6].p Yes Yes T142,T145,T147 Yes T136,T143,T144 OUTPUT
alert_req_o.alerts[7].n Yes Yes T136,T143,T144 Yes T145,T147,T146 OUTPUT
alert_req_o.alerts[7].p Yes Yes T145,T147,T146 Yes T136,T143,T144 OUTPUT
alert_req_o.alerts[8].n Yes Yes T136,T143,T144 Yes T145,T147,T146 OUTPUT
alert_req_o.alerts[8].p Yes Yes T145,T147,T146 Yes T136,T143,T144 OUTPUT
alert_req_o.alerts[9].n Yes Yes T136,T143,T144 Yes T146,T148 OUTPUT
alert_req_o.alerts[9].p Yes Yes T146,T148 Yes T136,T143,T144 OUTPUT
alert_req_o.alerts[10].n Yes Yes T136,T143,T144 Yes T142,T145,T147 OUTPUT
alert_req_o.alerts[10].p Yes Yes T142,T145,T147 Yes T136,T143,T144 OUTPUT
dft_strap_test_i.straps[0] No No Yes T75 INPUT
dft_strap_test_i.straps[1] No No No INPUT
dft_strap_test_i.valid Yes Yes T45,T46,T47 Yes T5,T6,T17 INPUT
lc_dft_en_i[3:0] Yes Yes T45,T46,T47 Yes T5,T6,T17 INPUT
fla_obs_i[7:0] Unreachable Unreachable Unreachable INPUT
otp_obs_i[7:0] Unreachable Unreachable Unreachable INPUT
otm_obs_i[7:0] Unreachable Unreachable Unreachable INPUT
usb_obs_i Yes Yes T69,T36,T37 Yes T69,T36,T37 INPUT
obs_ctrl_o.obmen[3:0] No No No OUTPUT
obs_ctrl_o.obmsl[3:0] No No No OUTPUT
obs_ctrl_o.obgsl[3:0] No No No OUTPUT
padmux2ast_i[7:0] Yes Yes T1,T118,T154 Yes T1,T118,T23 INPUT
ast2padmux_o[8:0] Unreachable Unreachable Unreachable OUTPUT
mux_iob_sel_o[3:0] Unreachable Unreachable Unreachable OUTPUT
ast2pad_t0_ao Yes Yes T1,T119,T3 Yes T1,T119,T3 OUTPUT
ast2pad_t1_ao Yes Yes T1,T3,T11 Yes T1,T3,T11 OUTPUT
ext_freq_is_96m_i[3:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
all_clk_byp_req_i[3:0] Yes Yes T128,T129,T130 Yes T128,T129,T131 INPUT
all_clk_byp_ack_o[3:0] Yes Yes T128,T129,T130 Yes T128,T129,T131 OUTPUT
io_clk_byp_req_i[3:0] Yes Yes T22,T63,T72 Yes T22,T63,T72 INPUT
io_clk_byp_ack_o[3:0] Yes Yes T22,T63,T72 Yes T22,T63,T72 OUTPUT
flash_bist_en_o[3:0] Unreachable Unreachable Unreachable OUTPUT
dpram_rmf_o.marg_b[3:0] No No No OUTPUT
dpram_rmf_o.marg_en_b No No No OUTPUT
dpram_rmf_o.test_b No No No OUTPUT
dpram_rmf_o.marg_a[3:0] No No No OUTPUT
dpram_rmf_o.marg_en_a No No No OUTPUT
dpram_rmf_o.test_a No No No OUTPUT
dpram_rml_o.marg_b[3:0] No No No OUTPUT
dpram_rml_o.marg_en_b No No No OUTPUT
dpram_rml_o.test_b No No No OUTPUT
dpram_rml_o.marg_a[3:0] No No No OUTPUT
dpram_rml_o.marg_en_a No No No OUTPUT
dpram_rml_o.test_a No No No OUTPUT
spram_rm_o.marg[3:0] No No No OUTPUT
spram_rm_o.marg_en No No No OUTPUT
spram_rm_o.test No No No OUTPUT
sprgf_rm_o.marg[3:0] No No No OUTPUT
sprgf_rm_o.marg_en No No No OUTPUT
sprgf_rm_o.test No No No OUTPUT
sprom_rm_o.marg[3:0] No No No OUTPUT
sprom_rm_o.marg_en No No No OUTPUT
sprom_rm_o.test No No No OUTPUT
dft_scan_md_o[3:0] Unreachable Unreachable Unreachable OUTPUT
scan_shift_en_o Unreachable Unreachable Unreachable OUTPUT
scan_reset_no Unreachable Unreachable Unreachable OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ast
TotalCoveredPercent
Totals 214 183 85.51
Total Bits 878 818 93.17
Total Bits 0->1 439 412 93.85
Total Bits 1->0 439 406 92.48

Ports 214 183 85.51
Port Bits 878 818 93.17
Port Bits 0->1 439 412 93.85
Port Bits 1->0 439 406 92.48

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
tl_i.d_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_address[9:0] Yes Yes *T87,*T88,*T89 Yes T87,T88,T89 INPUT
tl_i.a_address[18:10] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[21:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T80,T90,T65 Yes T80,T90,T65 INPUT
tl_i.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_o.a_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_o.d_error Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T88,T135,T89 Yes T88,T135,T89 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T45,T46,T47 Yes T5,T6,T17 OUTPUT
tl_o.d_data[31:0] Yes Yes T45,T46,T47 Yes T5,T6,T17 OUTPUT
tl_o.d_sink Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_source[5:0] Yes Yes *T88,*T89,*T91 Yes T88,T89,T91 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T88,*T135,*T89 Yes T88,T135,T89 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
ast_init_done_o[3:0] Yes Yes T5,T6,T17 Yes T45,T46,T47 OUTPUT
clk_ast_adc_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_adc_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
clk_ast_alert_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_alert_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
clk_ast_es_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_es_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
clk_ast_rng_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_rng_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
clk_ast_tlul_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_tlul_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
clk_ast_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_usb_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
clk_ast_ext_i Yes Yes T22,T63,T72 Yes T22,T23,T63 INPUT
por_ni Yes Yes T20,T21,T22 Yes T4,T5,T6 INPUT
sns_clks_i.clk_usb_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div2_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div4_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div4_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div4_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div2_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_usb_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div4_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_otbn Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_kmac Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_hmac Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_aes Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div2_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_usb_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div4_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_i2c2_n[0] No No No INPUT
sns_rsts_i.rst_i2c2_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_i2c1_n[0] No No No INPUT
sns_rsts_i.rst_i2c1_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_i2c0_n[0] No No No INPUT
sns_rsts_i.rst_i2c0_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_usb_aon_n[0] No No No INPUT
sns_rsts_i.rst_usb_aon_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_usb_n[0] No No No INPUT
sns_rsts_i.rst_usb_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_spi_host1_n[0] No No No INPUT
sns_rsts_i.rst_spi_host1_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_spi_host0_n[0] No No No INPUT
sns_rsts_i.rst_spi_host0_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_spi_device_n[0] No No No INPUT
sns_rsts_i.rst_spi_device_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_sys_io_div4_n[0] Yes Yes *T45,*T46,*T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_sys_io_div4_n[1] No No No INPUT
sns_rsts_i.rst_sys_n[0] No No No INPUT
sns_rsts_i.rst_sys_n[1] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_usb_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_io_div4_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_io_div4_shadowed_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_io_div2_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_io_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_aon_n[0] Yes Yes *T45,*T46,*T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_aon_n[1] No No No INPUT
sns_rsts_i.rst_lc_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_lc_shadowed_n[1:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_usb_n[0] Yes Yes *T20,*T21,*T22 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_usb_n[1] No No No INPUT
sns_rsts_i.rst_por_io_div4_n[0] Yes Yes *T20,*T21,*T22 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_io_div4_n[1] No No No INPUT
sns_rsts_i.rst_por_io_div2_n[0] Yes Yes *T20,*T21,*T22 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_io_div2_n[1] No No No INPUT
sns_rsts_i.rst_por_io_n[0] Yes Yes *T20,*T21,*T22 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_io_n[1] No No No INPUT
sns_rsts_i.rst_por_n[0] Yes Yes *T20,*T21,*T22 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_n[1] No No No INPUT
sns_rsts_i.rst_por_aon_n[1:0] Yes Yes T20,T21,T22 Yes T4,T5,T6 INPUT
sns_spi_ext_clk_i Yes Yes T26,T76,T27 Yes T26,T23,T76 INPUT
vcc_supp_i Unreachable Unreachable Unreachable INPUT
vcaon_supp_i Unreachable Unreachable Unreachable INPUT
vcmain_supp_i Unreachable Unreachable Unreachable INPUT
vioa_supp_i Unreachable Unreachable Unreachable INPUT
viob_supp_i Unreachable Unreachable Unreachable INPUT
ast_pwst_o.io_pok[1:0] Yes Yes T149,T150,T151 Yes T4,T5,T6 OUTPUT
ast_pwst_o.main_pok Yes Yes T103,T20,T21 Yes T4,T5,T6 OUTPUT
ast_pwst_o.vcc_pok No No Yes T4,T5,T6 OUTPUT
ast_pwst_o.aon_pok Yes Yes T20,T21,T22 Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.io_pok[1:0] Yes Yes T149,T150,T151 Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.main_pok Yes Yes T103,T20,T21 Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.vcc_pok No No Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.aon_pok Yes Yes T20,T21,T22 Yes T4,T5,T6 OUTPUT
main_pd_ni Yes Yes T103,T132,T31 Yes T103,T132,T31 INPUT
main_env_iso_en_i Yes Yes T4,T5,T6 Yes T103,T20,T21 INPUT
flash_power_down_h_o Yes Yes T4,T5,T6 Yes T103,T132,T31 OUTPUT
flash_power_ready_h_o No No Yes T4,T5,T6 OUTPUT
otp_power_seq_i[1:0] No No No INPUT
otp_power_seq_h_o[0] No No No OUTPUT
otp_power_seq_h_o[1] Yes Yes T4,T5,T6 Yes T103,T132,T31 OUTPUT
clk_src_sys_en_i Yes Yes T19,T70,T71 Yes T4,T5,T6 INPUT
clk_src_sys_jen_i[3:0] Yes Yes T17,T46,T126 Yes T46,T127,T125 INPUT
clk_src_sys_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_sys_val_o Yes Yes T19,T70,T71 Yes T4,T5,T6 OUTPUT
clk_src_aon_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_aon_val_o Yes Yes T128,T129,T130 Yes T4,T5,T6 OUTPUT
clk_src_io_en_i Yes Yes T19,T70,T71 Yes T4,T5,T6 INPUT
clk_src_io_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_io_val_o Yes Yes T19,T70,T71 Yes T4,T5,T6 OUTPUT
clk_src_io_48m_o[3:0] Yes Yes T22,T63,T72 Yes T22,T63,T72 OUTPUT
usb_ref_pulse_i Yes Yes T36,T37,T38 Yes T36,T37,T38 INPUT
usb_ref_val_i Yes Yes T36,T37,T38 Yes T36,T37,T38 INPUT
clk_src_usb_en_i Yes Yes T19,T70,T71 Yes T4,T5,T6 INPUT
clk_src_usb_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_usb_val_o Yes Yes T19,T70,T71 Yes T4,T5,T6 OUTPUT
usb_io_pu_cal_o[19:0] Unreachable Unreachable Unreachable OUTPUT
adc_pd_i Yes Yes T103,T2,T119 Yes T103,T2,T119 INPUT
adc_a0_ai No No Yes T23,T24,T25 INPUT
adc_a1_ai No No Yes T23,T24,T25 INPUT
adc_chnsel_i[1:0] Yes Yes T103,T2,T119 Yes T103,T2,T119 INPUT
adc_d_o[9:0] Yes Yes T103,T2,T120 Yes T103,T2,T120 OUTPUT
adc_d_val_o Yes Yes T103,T2,T119 Yes T103,T2,T119 OUTPUT
rng_en_i Yes Yes T45,T46,T47 Yes T5,T6,T17 INPUT
rng_fips_i Yes Yes T115,T133,T134 Yes T45,T46,T105 INPUT
rng_val_o Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
rng_b_o[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
entropy_rsp_i.edn_bus[31:0] Yes Yes T17,T26,T97 Yes T5,T6,T17 INPUT
entropy_rsp_i.edn_fips Yes Yes T121,T122,T123 Yes T46,T124,T125 INPUT
entropy_rsp_i.edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
entropy_req_o.edn_req Yes Yes T5,T6,T17 Yes T4,T5,T6 OUTPUT
alert_rsp_i.alerts_trig[0].n Yes Yes T2,T136,T137 Yes T2,T136,T137 INPUT
alert_rsp_i.alerts_trig[0].p Yes Yes T2,T136,T137 Yes T2,T136,T137 INPUT
alert_rsp_i.alerts_trig[1].n Yes Yes T136,T138,T139 Yes T136,T138,T139 INPUT
alert_rsp_i.alerts_trig[1].p Yes Yes T136,T138,T139 Yes T136,T138,T139 INPUT
alert_rsp_i.alerts_trig[2].n Yes Yes T136,T137,T141 Yes T136,T137,T141 INPUT
alert_rsp_i.alerts_trig[2].p Yes Yes T136,T137,T141 Yes T136,T137,T141 INPUT
alert_rsp_i.alerts_trig[3].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[3].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[4].n Yes Yes T136,T137,T138 Yes T136,T137,T138 INPUT
alert_rsp_i.alerts_trig[4].p Yes Yes T136,T137,T138 Yes T136,T137,T138 INPUT
alert_rsp_i.alerts_trig[5].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[5].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[6].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[6].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[7].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[7].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[8].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[8].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[9].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[9].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[10].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_trig[10].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[0].n Yes Yes T2,T136,T137 Yes T2,T136,T137 INPUT
alert_rsp_i.alerts_ack[0].p Yes Yes T2,T136,T137 Yes T2,T136,T137 INPUT
alert_rsp_i.alerts_ack[1].n Yes Yes T136,T138,T139 Yes T136,T138,T139 INPUT
alert_rsp_i.alerts_ack[1].p Yes Yes T136,T138,T139 Yes T136,T138,T139 INPUT
alert_rsp_i.alerts_ack[2].n Yes Yes T136,T137,T141 Yes T136,T137,T141 INPUT
alert_rsp_i.alerts_ack[2].p Yes Yes T136,T137,T141 Yes T136,T137,T141 INPUT
alert_rsp_i.alerts_ack[3].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[3].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[4].n Yes Yes T136,T137,T138 Yes T136,T137,T138 INPUT
alert_rsp_i.alerts_ack[4].p Yes Yes T136,T137,T138 Yes T136,T137,T138 INPUT
alert_rsp_i.alerts_ack[5].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[5].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[6].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[6].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[7].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[7].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[8].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[8].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[9].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[9].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[10].n Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_rsp_i.alerts_ack[10].p Yes Yes T136,T143,T144 Yes T136,T143,T144 INPUT
alert_req_o.alerts[0].n Yes Yes T2,T136,T137 Yes T2,T137,T14 OUTPUT
alert_req_o.alerts[0].p Yes Yes T2,T137,T14 Yes T2,T136,T137 OUTPUT
alert_req_o.alerts[1].n Yes Yes T136,T138,T139 Yes T138,T139,T140 OUTPUT
alert_req_o.alerts[1].p Yes Yes T138,T139,T140 Yes T136,T138,T139 OUTPUT
alert_req_o.alerts[2].n Yes Yes T136,T137,T141 Yes T137,T141,T142 OUTPUT
alert_req_o.alerts[2].p Yes Yes T137,T141,T142 Yes T136,T137,T141 OUTPUT
alert_req_o.alerts[3].n Yes Yes T136,T143,T144 Yes T145,T146 OUTPUT
alert_req_o.alerts[3].p Yes Yes T145,T146 Yes T136,T143,T144 OUTPUT
alert_req_o.alerts[4].n Yes Yes T136,T137,T138 Yes T137,T138,T139 OUTPUT
alert_req_o.alerts[4].p Yes Yes T137,T138,T139 Yes T136,T137,T138 OUTPUT
alert_req_o.alerts[5].n Yes Yes T136,T143,T144 Yes T142,T145,T146 OUTPUT
alert_req_o.alerts[5].p Yes Yes T142,T145,T146 Yes T136,T143,T144 OUTPUT
alert_req_o.alerts[6].n Yes Yes T136,T143,T144 Yes T142,T145,T147 OUTPUT
alert_req_o.alerts[6].p Yes Yes T142,T145,T147 Yes T136,T143,T144 OUTPUT
alert_req_o.alerts[7].n Yes Yes T136,T143,T144 Yes T145,T147,T146 OUTPUT
alert_req_o.alerts[7].p Yes Yes T145,T147,T146 Yes T136,T143,T144 OUTPUT
alert_req_o.alerts[8].n Yes Yes T136,T143,T144 Yes T145,T147,T146 OUTPUT
alert_req_o.alerts[8].p Yes Yes T145,T147,T146 Yes T136,T143,T144 OUTPUT
alert_req_o.alerts[9].n Yes Yes T136,T143,T144 Yes T146,T148 OUTPUT
alert_req_o.alerts[9].p Yes Yes T146,T148 Yes T136,T143,T144 OUTPUT
alert_req_o.alerts[10].n Yes Yes T136,T143,T144 Yes T142,T145,T147 OUTPUT
alert_req_o.alerts[10].p Yes Yes T142,T145,T147 Yes T136,T143,T144 OUTPUT
dft_strap_test_i.straps[0] No No Yes T75 INPUT
dft_strap_test_i.straps[1] No No No INPUT
dft_strap_test_i.valid Yes Yes T45,T46,T47 Yes T5,T6,T17 INPUT
lc_dft_en_i[3:0] Yes Yes T45,T46,T47 Yes T5,T6,T17 INPUT
fla_obs_i[7:0] Unreachable Unreachable Unreachable INPUT
otp_obs_i[7:0] Unreachable Unreachable Unreachable INPUT
otm_obs_i[7:0] Unreachable Unreachable Unreachable INPUT
usb_obs_i Yes Yes T69,T36,T37 Yes T69,T36,T37 INPUT
obs_ctrl_o.obmen[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_o.obmsl[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_o.obgsl[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
padmux2ast_i[7:0] Yes Yes T1,T118,T154 Yes T1,T118,T23 INPUT
ast2padmux_o[8:0] Unreachable Unreachable Unreachable OUTPUT
mux_iob_sel_o[3:0] Unreachable Unreachable Unreachable OUTPUT
ast2pad_t0_ao Yes Yes T1,T119,T3 Yes T1,T119,T3 OUTPUT
ast2pad_t1_ao Yes Yes T1,T3,T11 Yes T1,T3,T11 OUTPUT
ext_freq_is_96m_i[3:0] Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
all_clk_byp_req_i[3:0] Yes Yes T128,T129,T130 Yes T128,T129,T131 INPUT
all_clk_byp_ack_o[3:0] Yes Yes T128,T129,T130 Yes T128,T129,T131 OUTPUT
io_clk_byp_req_i[3:0] Yes Yes T22,T63,T72 Yes T22,T63,T72 INPUT
io_clk_byp_ack_o[3:0] Yes Yes T22,T63,T72 Yes T22,T63,T72 OUTPUT
flash_bist_en_o[3:0] Unreachable Unreachable Unreachable OUTPUT
dpram_rmf_o.marg_b[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rmf_o.marg_en_b[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rmf_o.test_b No No No OUTPUT
dpram_rmf_o.marg_a[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rmf_o.marg_en_a[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rmf_o.test_a No No No OUTPUT
dpram_rml_o.marg_b[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rml_o.marg_en_b[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rml_o.test_b No No No OUTPUT
dpram_rml_o.marg_a[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rml_o.marg_en_a[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rml_o.test_a No No No OUTPUT
spram_rm_o.marg[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
spram_rm_o.marg_en[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
spram_rm_o.test No No No OUTPUT
sprgf_rm_o.marg[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sprgf_rm_o.marg_en[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sprgf_rm_o.test No No No OUTPUT
sprom_rm_o.marg[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sprom_rm_o.marg_en[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sprom_rm_o.test No No No OUTPUT
dft_scan_md_o[3:0] Unreachable Unreachable Unreachable OUTPUT
scan_shift_en_o Unreachable Unreachable Unreachable OUTPUT
scan_reset_no Unreachable Unreachable Unreachable OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%