Module Definition
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Cond Coverage for Module : tlul_fifo_sync
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T17

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T17

Branch Coverage for Module : tlul_fifo_sync
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T17
0 Covered T4,T5,T6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%