Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spi_device
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.57 86.57

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_spi_device 96.39 96.39


Module Instance : tb.dut.top_earlgrey.u_spi_device

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.39 96.39


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.39 96.39


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.21 90.32 89.30 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : spi_device
TotalCoveredPercent
Totals 65 50 76.92
Total Bits 432 374 86.57
Total Bits 0->1 216 187 86.57
Total Bits 1->0 216 187 86.57

Ports 65 50 76.92
Port Bits 432 374 86.57
Port Bits 0->1 216 187 86.57
Port Bits 1->0 216 187 86.57

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T26,T76,T206 Yes T26,T76,T206 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T26,T76,T206 Yes T26,T76,T206 INPUT
tl_i.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_address[12:0] Yes Yes *T87,*T88,*T89 Yes T87,T88,T89 INPUT
tl_i.a_address[15:13] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[29:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T80,T90,T65 Yes T80,T90,T65 INPUT
tl_i.a_valid Yes Yes T26,T76,T66 Yes T26,T76,T66 INPUT
tl_o.a_ready Yes Yes T26,T76,T66 Yes T26,T76,T66 OUTPUT
tl_o.d_error Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T26,T76,T206 Yes T26,T76,T206 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T26,T76,T206 Yes T26,T76,T206 OUTPUT
tl_o.d_data[31:0] Yes Yes T26,T76,T66 Yes T26,T76,T206 OUTPUT
tl_o.d_sink Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_source[5:0] Yes Yes *T88,*T89,*T91 Yes T88,T89,T91 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T26,*T76,*T66 Yes T26,T76,T206 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T26,T76,T66 Yes T26,T76,T66 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T117,T207,T66 Yes T117,T207,T66 INPUT
alert_rx_i[0].ping_n Yes Yes T186,T208,T93 Yes T186,T208,T93 INPUT
alert_rx_i[0].ping_p Yes Yes T186,T208,T93 Yes T186,T208,T93 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T117,T207,T66 Yes T117,T207,T66 OUTPUT
cio_sck_i Yes Yes T26,T76,T27 Yes T26,T23,T76 INPUT
cio_csb_i Yes Yes T26,T23,T76 Yes T26,T23,T76 INPUT
cio_sd_o[3:0] Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
cio_sd_en_o[3:0] Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
cio_sd_i[3:0] Yes Yes T26,T76,T27 Yes T26,T76,T27 INPUT
cio_tpm_csb_i Yes Yes T54,T55,T56 Yes T54,T55,T56 INPUT
passthrough_o.s_en[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
passthrough_o.s_en[3:1] No No No OUTPUT
passthrough_o.s[3:0] Yes Yes T26,T76,T27 Yes T26,T76,T27 OUTPUT
passthrough_o.csb_en No No No OUTPUT
passthrough_o.csb Yes Yes T26,T23,T76 Yes T26,T23,T76 OUTPUT
passthrough_o.sck_en No No No OUTPUT
passthrough_o.sck Yes Yes T26,T76,T27 Yes T26,T76,T27 OUTPUT
passthrough_o.passthrough_en Yes Yes T27,T168,T170 Yes T26,T27,T28 OUTPUT
passthrough_i.s[3:0] Yes Yes T26,T27,T28 Yes T26,T27,T28 INPUT
intr_upload_cmdfifo_not_empty_o Yes Yes T27,T168,T180 Yes T27,T168,T180 OUTPUT
intr_upload_payload_not_empty_o Yes Yes T180,T181,T182 Yes T180,T181,T182 OUTPUT
intr_upload_payload_overflow_o Yes Yes T180,T181,T182 Yes T180,T181,T182 OUTPUT
intr_readbuf_watermark_o Yes Yes T180,T181,T182 Yes T180,T181,T182 OUTPUT
intr_readbuf_flip_o Yes Yes T180,T181,T182 Yes T180,T181,T182 OUTPUT
intr_tpm_header_not_empty_o Yes Yes T54,T55,T56 Yes T54,T55,T56 OUTPUT
intr_tpm_rdfifo_cmd_end_o Yes Yes T180,T181,T182 Yes T180,T181,T182 OUTPUT
intr_tpm_rdfifo_drop_o Yes Yes T180,T181,T182 Yes T180,T181,T182 OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0] No No No INPUT
ram_cfg_i.b_ram_lcfg.cfg_en No No No INPUT
ram_cfg_i.b_ram_lcfg.test No No No INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0] No No No INPUT
ram_cfg_i.a_ram_lcfg.cfg_en No No No INPUT
ram_cfg_i.a_ram_lcfg.test No No No INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0] No No No INPUT
ram_cfg_i.b_ram_fcfg.cfg_en No No No INPUT
ram_cfg_i.b_ram_fcfg.test No No No INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0] No No No INPUT
ram_cfg_i.a_ram_fcfg.cfg_en No No No INPUT
ram_cfg_i.a_ram_fcfg.test No No No INPUT
sck_monitor_o Yes Yes T26,T76,T27 Yes T26,T23,T76 OUTPUT
mbist_en_i Unreachable Unreachable Unreachable INPUT
scan_clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_device
TotalCoveredPercent
Totals 55 50 90.91
Total Bits 388 374 96.39
Total Bits 0->1 194 187 96.39
Total Bits 1->0 194 187 96.39

Ports 55 50 90.91
Port Bits 388 374 96.39
Port Bits 0->1 194 187 96.39
Port Bits 1->0 194 187 96.39

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T26,T76,T206 Yes T26,T76,T206 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T26,T76,T206 Yes T26,T76,T206 INPUT
tl_i.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_address[12:0] Yes Yes *T87,*T88,*T89 Yes T87,T88,T89 INPUT
tl_i.a_address[15:13] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[29:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T80,T90,T65 Yes T80,T90,T65 INPUT
tl_i.a_valid Yes Yes T26,T76,T66 Yes T26,T76,T66 INPUT
tl_o.a_ready Yes Yes T26,T76,T66 Yes T26,T76,T66 OUTPUT
tl_o.d_error Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T26,T76,T206 Yes T26,T76,T206 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T26,T76,T206 Yes T26,T76,T206 OUTPUT
tl_o.d_data[31:0] Yes Yes T26,T76,T66 Yes T26,T76,T206 OUTPUT
tl_o.d_sink Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_source[5:0] Yes Yes *T88,*T89,*T91 Yes T88,T89,T91 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T26,*T76,*T66 Yes T26,T76,T206 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T26,T76,T66 Yes T26,T76,T66 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T117,T207,T66 Yes T117,T207,T66 INPUT
alert_rx_i[0].ping_n Yes Yes T186,T208,T93 Yes T186,T208,T93 INPUT
alert_rx_i[0].ping_p Yes Yes T186,T208,T93 Yes T186,T208,T93 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T117,T207,T66 Yes T117,T207,T66 OUTPUT
cio_sck_i Yes Yes T26,T76,T27 Yes T26,T23,T76 INPUT
cio_csb_i Yes Yes T26,T23,T76 Yes T26,T23,T76 INPUT
cio_sd_o[3:0] Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
cio_sd_en_o[3:0] Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
cio_sd_i[3:0] Yes Yes T26,T76,T27 Yes T26,T76,T27 INPUT
cio_tpm_csb_i Yes Yes T54,T55,T56 Yes T54,T55,T56 INPUT
passthrough_o.s_en[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
passthrough_o.s_en[3:1] No No No OUTPUT
passthrough_o.s[3:0] Yes Yes T26,T76,T27 Yes T26,T76,T27 OUTPUT
passthrough_o.csb_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off.
passthrough_o.csb Yes Yes T26,T23,T76 Yes T26,T23,T76 OUTPUT
passthrough_o.sck_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off.
passthrough_o.sck Yes Yes T26,T76,T27 Yes T26,T76,T27 OUTPUT
passthrough_o.passthrough_en Yes Yes T27,T168,T170 Yes T26,T27,T28 OUTPUT
passthrough_i.s[3:0] Yes Yes T26,T27,T28 Yes T26,T27,T28 INPUT
intr_upload_cmdfifo_not_empty_o Yes Yes T27,T168,T180 Yes T27,T168,T180 OUTPUT
intr_upload_payload_not_empty_o Yes Yes T180,T181,T182 Yes T180,T181,T182 OUTPUT
intr_upload_payload_overflow_o Yes Yes T180,T181,T182 Yes T180,T181,T182 OUTPUT
intr_readbuf_watermark_o Yes Yes T180,T181,T182 Yes T180,T181,T182 OUTPUT
intr_readbuf_flip_o Yes Yes T180,T181,T182 Yes T180,T181,T182 OUTPUT
intr_tpm_header_not_empty_o Yes Yes T54,T55,T56 Yes T54,T55,T56 OUTPUT
intr_tpm_rdfifo_cmd_end_o Yes Yes T180,T181,T182 Yes T180,T181,T182 OUTPUT
intr_tpm_rdfifo_drop_o Yes Yes T180,T181,T182 Yes T180,T181,T182 OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_lcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_lcfg.test No No No INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.test No No No INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.test No No No INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.test No No No INPUT
sck_monitor_o Yes Yes T26,T76,T27 Yes T26,T23,T76 OUTPUT
mbist_en_i Unreachable Unreachable Unreachable INPUT
scan_clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%