Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
clk_lc_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
INPUT |
rst_lc_ni |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
INPUT |
next_dm_addr_i[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
lc_hw_debug_en_i[3:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T5,T6,T17 |
INPUT |
lc_dft_en_i[3:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T5,T6,T17 |
INPUT |
pinmux_hw_debug_en_i[3:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T5,T6,T17 |
INPUT |
otp_dis_rv_dm_late_debug_i[7:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T45,T46,T47 |
INPUT |
scanmode_i[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
scan_rst_ni |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
ndmreset_req_o |
Yes |
Yes |
T7,T349,T8 |
Yes |
T7,T349,T8 |
OUTPUT |
dmactive_o |
Yes |
Yes |
T76,T79,T80 |
Yes |
T76,T77,T78 |
OUTPUT |
debug_req_o |
Yes |
Yes |
T77,T78,T256 |
Yes |
T77,T78,T256 |
OUTPUT |
unavailable_i |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_d_i.d_ready |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
INPUT |
regs_tl_d_i.a_user.data_intg[6:0] |
Yes |
Yes |
T87,T88,T135 |
Yes |
T87,T88,T135 |
INPUT |
regs_tl_d_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T87,T88,T135 |
Yes |
T87,T88,T135 |
INPUT |
regs_tl_d_i.a_user.instr_type[3:0] |
Yes |
Yes |
T87,T88,T135 |
Yes |
T87,T88,T135 |
INPUT |
regs_tl_d_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_d_i.a_data[31:0] |
Yes |
Yes |
T87,T88,T135 |
Yes |
T87,T88,T135 |
INPUT |
regs_tl_d_i.a_mask[3:0] |
Yes |
Yes |
T87,T88,T135 |
Yes |
T87,T88,T135 |
INPUT |
regs_tl_d_i.a_address[3:0] |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
INPUT |
regs_tl_d_i.a_address[20:4] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_d_i.a_address[21] |
Yes |
Yes |
*T87,*T88,*T135 |
Yes |
T87,T88,T135 |
INPUT |
regs_tl_d_i.a_address[23:22] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_d_i.a_address[24] |
Yes |
Yes |
*T87,*T88,*T135 |
Yes |
T87,T88,T135 |
INPUT |
regs_tl_d_i.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_d_i.a_address[30] |
Yes |
Yes |
*T87,*T88,*T135 |
Yes |
T87,T88,T135 |
INPUT |
regs_tl_d_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_d_i.a_source[5:0] |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
INPUT |
regs_tl_d_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_d_i.a_size[1:0] |
Yes |
Yes |
T87,T88,T89 |
Yes |
T87,T88,T89 |
INPUT |
regs_tl_d_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_d_i.a_opcode[2:0] |
Yes |
Yes |
T87,T88,T135 |
Yes |
T87,T88,T135 |
INPUT |
regs_tl_d_i.a_valid |
Yes |
Yes |
T87,T88,T135 |
Yes |
T87,T88,T135 |
INPUT |
regs_tl_d_o.a_ready |
Yes |
Yes |
T87,T88,T135 |
Yes |
T87,T88,T135 |
OUTPUT |
regs_tl_d_o.d_error |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
OUTPUT |
regs_tl_d_o.d_user.data_intg[6:0] |
Yes |
Yes |
T87,T88,T135 |
Yes |
T87,T88,T135 |
OUTPUT |
regs_tl_d_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T87,T88,T135 |
Yes |
T87,T88,T135 |
OUTPUT |
regs_tl_d_o.d_data[31:0] |
Yes |
Yes |
T87,T88,T135 |
Yes |
T87,T88,T135 |
OUTPUT |
regs_tl_d_o.d_sink |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
OUTPUT |
regs_tl_d_o.d_source[5:0] |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
OUTPUT |
regs_tl_d_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_d_o.d_size[1:0] |
Yes |
Yes |
T87,T88,T89 |
Yes |
T87,T88,T89 |
OUTPUT |
regs_tl_d_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_d_o.d_opcode[0] |
Yes |
Yes |
*T87,*T88,*T135 |
Yes |
T87,T88,T135 |
OUTPUT |
regs_tl_d_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_d_o.d_valid |
Yes |
Yes |
T87,T88,T135 |
Yes |
T87,T88,T135 |
OUTPUT |
mem_tl_d_i.d_ready |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
INPUT |
mem_tl_d_i.a_user.data_intg[6:0] |
Yes |
Yes |
T77,T78,T256 |
Yes |
T77,T78,T256 |
INPUT |
mem_tl_d_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T77,T78,T256 |
Yes |
T77,T78,T256 |
INPUT |
mem_tl_d_i.a_user.instr_type[3:0] |
Yes |
Yes |
T77,T78,T256 |
Yes |
T77,T78,T256 |
INPUT |
mem_tl_d_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
mem_tl_d_i.a_data[31:0] |
Yes |
Yes |
T77,T78,T256 |
Yes |
T77,T78,T256 |
INPUT |
mem_tl_d_i.a_mask[3:0] |
Yes |
Yes |
T77,T78,T256 |
Yes |
T77,T78,T256 |
INPUT |
mem_tl_d_i.a_address[11:0] |
Yes |
Yes |
*T87,T88,T89 |
Yes |
T87,T88,T89 |
INPUT |
mem_tl_d_i.a_address[15:12] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
mem_tl_d_i.a_address[16] |
Yes |
Yes |
*T77,*T78,*T256 |
Yes |
T77,T78,T256 |
INPUT |
mem_tl_d_i.a_address[31:17] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
mem_tl_d_i.a_source[5:0] |
Yes |
Yes |
*T77,*T78,*T256 |
Yes |
T77,T78,T256 |
INPUT |
mem_tl_d_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
mem_tl_d_i.a_size[1:0] |
Yes |
Yes |
T87,T88,T89 |
Yes |
T87,T88,T89 |
INPUT |
mem_tl_d_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
mem_tl_d_i.a_opcode[2:0] |
Yes |
Yes |
T87,T88,T135 |
Yes |
T87,T88,T135 |
INPUT |
mem_tl_d_i.a_valid |
Yes |
Yes |
T77,T78,T256 |
Yes |
T77,T78,T256 |
INPUT |
mem_tl_d_o.a_ready |
Yes |
Yes |
T5,T6,T17 |
Yes |
T5,T6,T17 |
OUTPUT |
mem_tl_d_o.d_error |
Yes |
Yes |
T5,T6,T17 |
Yes |
T45,T46,T47 |
OUTPUT |
mem_tl_d_o.d_user.data_intg[6:0] |
Yes |
Yes |
T77,T78,T256 |
Yes |
T77,T78,T256 |
OUTPUT |
mem_tl_d_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T77,T78,T256 |
Yes |
T77,T78,T256 |
OUTPUT |
mem_tl_d_o.d_data[31:0] |
Yes |
Yes |
T5,T6,T17 |
Yes |
T45,T46,T47 |
OUTPUT |
mem_tl_d_o.d_sink |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
OUTPUT |
mem_tl_d_o.d_source[5:0] |
Yes |
Yes |
*T77,*T78,*T256 |
Yes |
T77,T78,T256 |
OUTPUT |
mem_tl_d_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
mem_tl_d_o.d_size[1:0] |
Yes |
Yes |
T87,T88,T89 |
Yes |
T87,T88,T89 |
OUTPUT |
mem_tl_d_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
mem_tl_d_o.d_opcode[0] |
Yes |
Yes |
*T5,*T6,*T17 |
Yes |
T45,T46,T47 |
OUTPUT |
mem_tl_d_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
mem_tl_d_o.d_valid |
Yes |
Yes |
T77,T78,T256 |
Yes |
T77,T78,T256 |
OUTPUT |
sba_tl_h_o.d_ready |
Yes |
Yes |
T45,T46,T47 |
Yes |
T5,T6,T17 |
OUTPUT |
sba_tl_h_o.a_user.data_intg[6:0] |
Yes |
Yes |
T76,T78,T256 |
Yes |
T76,T78,T256 |
OUTPUT |
sba_tl_h_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T5,T6,T17 |
OUTPUT |
sba_tl_h_o.a_user.instr_type[3:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T5,T6,T17 |
OUTPUT |
sba_tl_h_o.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
sba_tl_h_o.a_data[31:0] |
Yes |
Yes |
T76,T78,T256 |
Yes |
T76,T78,T256 |
OUTPUT |
sba_tl_h_o.a_mask[3:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T5,T6,T17 |
OUTPUT |
sba_tl_h_o.a_address[31:0] |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
OUTPUT |
sba_tl_h_o.a_source[5:0] |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
OUTPUT |
sba_tl_h_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
sba_tl_h_o.a_size[1:0] |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
OUTPUT |
sba_tl_h_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
sba_tl_h_o.a_opcode[2:0] |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
OUTPUT |
sba_tl_h_o.a_valid |
Yes |
Yes |
T76,T77,T78 |
Yes |
T76,T77,T78 |
OUTPUT |
sba_tl_h_i.a_ready |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
INPUT |
sba_tl_h_i.d_error |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
INPUT |
sba_tl_h_i.d_user.data_intg[6:0] |
Yes |
Yes |
T76,T79,T80 |
Yes |
T76,T79,T80 |
INPUT |
sba_tl_h_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T76,T78,T256 |
Yes |
T76,T78,T256 |
INPUT |
sba_tl_h_i.d_data[31:0] |
Yes |
Yes |
T80,T81,T349 |
Yes |
T80,T81,T349 |
INPUT |
sba_tl_h_i.d_sink |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
INPUT |
sba_tl_h_i.d_source[5:0] |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
INPUT |
sba_tl_h_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
sba_tl_h_i.d_size[1:0] |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
INPUT |
sba_tl_h_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
sba_tl_h_i.d_opcode[0] |
Yes |
Yes |
*T76,*T77,*T78 |
Yes |
T76,T77,T78 |
INPUT |
sba_tl_h_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
sba_tl_h_i.d_valid |
Yes |
Yes |
T76,T77,T78 |
Yes |
T76,T77,T78 |
INPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T93,T94,T95 |
Yes |
T93,T94,T95 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T93,T94,T95 |
Yes |
T93,T94,T96 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T93,T94,T96 |
Yes |
T93,T94,T95 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T93,T94,T95 |
Yes |
T93,T94,T95 |
OUTPUT |
jtag_i.tdi |
Yes |
Yes |
T76,T77,T78 |
Yes |
T76,T77,T78 |
INPUT |
jtag_i.trst_n |
Yes |
Yes |
T76,T79,T80 |
Yes |
T76,T77,T78 |
INPUT |
jtag_i.tms |
Yes |
Yes |
T76,T77,T78 |
Yes |
T76,T77,T78 |
INPUT |
jtag_i.tck |
Yes |
Yes |
T76,T77,T78 |
Yes |
T76,T77,T78 |
INPUT |
jtag_o.tdo_oe |
Yes |
Yes |
T76,T77,T78 |
Yes |
T76,T77,T78 |
OUTPUT |
jtag_o.tdo |
Yes |
Yes |
T76,T77,T78 |
Yes |
T76,T77,T78 |
OUTPUT |