Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
INPUT |
clk_aon_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
clk_io_div4_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
clk_main_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
clk_io_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
clk_io_div2_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
clk_usb_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
clk_por_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_por_ni |
Yes |
Yes |
T20,T21,T22 |
Yes |
T4,T5,T6 |
INPUT |
por_n_i[1:0] |
Yes |
Yes |
T20,T21,T22 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T5,T6,T17 |
Yes |
T5,T6,T17 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T5,T6,T17 |
Yes |
T5,T6,T17 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T5,T6,T17 |
Yes |
T5,T6,T17 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T5,T6,T17 |
Yes |
T5,T6,T17 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T5,T17,T26 |
Yes |
T5,T17,T26 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T5,T6,T17 |
Yes |
T5,T6,T17 |
INPUT |
tl_i.a_address[6:0] |
Yes |
Yes |
*T87,*T88,*T89 |
Yes |
T87,T88,T89 |
INPUT |
tl_i.a_address[15:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[16] |
Yes |
Yes |
*T5,*T6,*T17 |
Yes |
T5,T6,T17 |
INPUT |
tl_i.a_address[21:17] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[22] |
Yes |
Yes |
*T5,*T6,*T17 |
Yes |
T5,T6,T17 |
INPUT |
tl_i.a_address[29:23] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T5,*T6,*T17 |
Yes |
T5,T6,T17 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T76,*T77,*T78 |
Yes |
T76,T77,T78 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T87,T88,T89 |
Yes |
T87,T88,T89 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T80,T90,T65 |
Yes |
T80,T90,T65 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T5,T6,T17 |
Yes |
T5,T6,T17 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T5,T6,T17 |
Yes |
T5,T6,T17 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T5,T6,T17 |
Yes |
T5,T6,T17 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T45,T59,T46 |
Yes |
T5,T6,T17 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T45,T59,T46 |
Yes |
T5,T6,T17 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T88,T89,T91 |
Yes |
T88,T89,T91 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T88,*T89,*T91 |
Yes |
T88,T89,T91 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T87,T88,T89 |
Yes |
T87,T88,T89 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T5,*T6,*T17 |
Yes |
T5,T6,T17 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T5,T6,T17 |
Yes |
T5,T6,T17 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T283,T66,T93 |
Yes |
T283,T66,T93 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T283,T93,T94 |
Yes |
T93,T94,T95 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T93,T94,T95 |
Yes |
T283,T93,T94 |
INPUT |
alert_rx_i[1].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[1].ack_p |
Yes |
Yes |
T66,T649,T93 |
Yes |
T66,T649,T93 |
INPUT |
alert_rx_i[1].ping_n |
Yes |
Yes |
T93,T94,T95 |
Yes |
T93,T94,T95 |
INPUT |
alert_rx_i[1].ping_p |
Yes |
Yes |
T93,T94,T95 |
Yes |
T93,T94,T95 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T283,T66,T93 |
Yes |
T283,T66,T93 |
OUTPUT |
alert_tx_o[1].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[1].alert_p |
Yes |
Yes |
T66,T649,T93 |
Yes |
T66,T649,T93 |
OUTPUT |
pwr_i.reset_cause[1:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T19,T45,T70 |
INPUT |
pwr_i.rstreqs[4:0] |
Yes |
Yes |
T218,T33,T305 |
Yes |
T218,T33,T305 |
INPUT |
pwr_i.rst_sys_req[1:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T45,T46,T47 |
INPUT |
pwr_i.rst_lc_req[1:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T45,T46,T47 |
INPUT |
pwr_o.rst_sys_src_n[1:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
OUTPUT |
pwr_o.rst_lc_src_n[1:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
OUTPUT |
sw_rst_req_o[3:0] |
Yes |
Yes |
T45,T46,T108 |
Yes |
T45,T46,T108 |
OUTPUT |
alert_dump_i.class_esc_cnt[3:0][31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_dump_i.class_accum_cnt[3:0][15:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_dump_i.loc_alert_cause[6:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_dump_i.alert_cause[64:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
cpu_dump_i.current.exception_addr[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
cpu_dump_i.current.exception_pc[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
cpu_dump_i.current.last_data_addr[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
cpu_dump_i.current.next_pc[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
cpu_dump_i.current.current_pc[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
cpu_dump_i.prev_exception_addr[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
cpu_dump_i.prev_exception_pc[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
cpu_dump_i.prev_valid |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
scan_rst_ni |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
scanmode_i[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
resets_o.rst_i2c2_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_i2c1_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_i2c0_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_usb_aon_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_usb_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_spi_host1_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_spi_host0_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_spi_device_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_sys_io_div4_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_sys_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_lc_usb_n[1:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
OUTPUT |
resets_o.rst_lc_io_div4_n[1:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
OUTPUT |
resets_o.rst_lc_io_div4_shadowed_n[1:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
OUTPUT |
resets_o.rst_lc_io_div2_n[1:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
OUTPUT |
resets_o.rst_lc_io_n[1:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
OUTPUT |
resets_o.rst_lc_aon_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_lc_n[1:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
OUTPUT |
resets_o.rst_lc_shadowed_n[1:0] |
Yes |
Yes |
T45,T46,T47 |
Yes |
T4,T5,T6 |
OUTPUT |
resets_o.rst_por_usb_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_por_io_div4_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_por_io_div2_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_por_io_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_por_n[1:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
resets_o.rst_por_aon_n[1:0] |
Yes |
Yes |
T20,T21,T22 |
Yes |
T4,T5,T6 |
OUTPUT |