Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| ALWAYS | 95 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 62 |
1 |
1 |
| 64 |
1 |
1 |
| 67 |
1 |
1 |
| 69 |
1 |
1 |
| 95 |
1 |
1 |
| 96 |
1 |
1 |
| 98 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr
| Total | Covered | Percent |
|---|
| Conditions | 12 | 12 | 100.00 |
| Logical | 12 | 12 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T180,T181,T182 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T180,T181,T182 |
| 1 | 1 | Covered | T180,T181,T182 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T150,T180,T151 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T150,T180,T151 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 95 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
IntrTKind_A |
1001 |
1001 |
0 |
0 |
IntrTKind_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1001 |
1001 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T26 |
1 |
1 |
0 |
0 |
| T45 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T97 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| ALWAYS | 95 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 62 |
1 |
1 |
| 64 |
1 |
1 |
| 67 |
1 |
1 |
| 69 |
1 |
1 |
| 95 |
1 |
1 |
| 96 |
1 |
1 |
| 98 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr
| Total | Covered | Percent |
|---|
| Conditions | 12 | 12 | 100.00 |
| Logical | 12 | 12 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T5,T6,T17 |
| 1 | 0 | Covered | T180,T181,T182 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T180,T181,T182 |
| 1 | 1 | Covered | T180,T181,T182 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T5,T6,T17 |
| 1 | 0 | Covered | T5,T6,T17 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T180,T181,T182 |
| 1 | 0 | Covered | T5,T6,T17 |
| 1 | 1 | Covered | T180,T181,T182 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 95 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
IntrTKind_A |
1001 |
1001 |
0 |
0 |
IntrTKind_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1001 |
1001 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T26 |
1 |
1 |
0 |
0 |
| T45 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T97 |
1 |
1 |
0 |
0 |