Unified Coverage Report :: Module :: pattgen

Module : pattgen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pattgen_0.1/rtl/pattgen.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pattgen	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pattgen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.21	90.32		89.30			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : pattgen

	Total	Covered	Percent
Totals	35	35	100.00
Total Bits	300	300	100.00
Total Bits 0->1	150	150	100.00
Total Bits 1->0	150	150	100.00

Ports	35	35	100.00
Port Bits	300	300	100.00
Port Bits 0->1	150	150	100.00
Port Bits 1->0	150	150	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T212,T213,T180	Yes	T212,T213,T180	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T212,T213,T180	Yes	T212,T213,T180	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T87,*T88,*T89	Yes	T87,T88,T89	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19:17]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	INPUT
tl_i.a_valid	Yes	Yes	T212,T66,T213	Yes	T212,T66,T213	INPUT
tl_o.a_ready	Yes	Yes	T212,T66,T213	Yes	T212,T66,T213	OUTPUT
tl_o.d_error	Yes	Yes	T88,T89,T250	Yes	T88,T89,T250	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T212,T213,T180	Yes	T212,T213,T180	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T212,T213,T180	Yes	T212,T66,T213	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T212,T213,T180	Yes	T212,T66,T213	OUTPUT
tl_o.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T65,*T92,T88	Yes	T65,T92,T88	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T212,*T213,*T180	Yes	T212,T213,T180	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T212,T66,T213	Yes	T212,T66,T213	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T656,T66,T336	Yes	T656,T66,T336	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T186,T93,T94	Yes	T186,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T186,T93,T94	Yes	T186,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T656,T66,T336	Yes	T656,T66,T336	OUTPUT
cio_pda0_tx_o	Yes	Yes	T65,T92,T135	Yes	T65,T92,T135	OUTPUT
cio_pcl0_tx_o	Yes	Yes	T87,T135,T152	Yes	T87,T135,T152	OUTPUT
cio_pda1_tx_o	Yes	Yes	T212,T213,T65	Yes	T212,T213,T65	OUTPUT
cio_pcl1_tx_o	Yes	Yes	T212,T213,T92	Yes	T212,T213,T92	OUTPUT
cio_pda0_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pcl0_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pda1_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pcl1_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_done_ch0_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_done_ch1_o	Yes	Yes	T212,T213,T180	Yes	T212,T213,T180	OUTPUT

*Tests covering at least one bit in the range