Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.21	90.32		89.30			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.21	90.32		89.30			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.21	90.32		89.30			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.21	90.32		89.30			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T87,*T88,*T89	Yes	T87,T88,T89	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	INPUT
tl_i.a_valid	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	INPUT
tl_o.a_ready	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
tl_o.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
tl_o.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T59,*T114	Yes	T5,T59,T114	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T71,T273,T658	Yes	T71,T273,T658	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T186,T341,T93	Yes	T186,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T186,T93,T94	Yes	T186,T341,T93	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T71,T273,T658	Yes	T71,T273,T658	OUTPUT
cio_rx_i	Yes	Yes	T5,T45,T46	Yes	T5,T6,T17	INPUT
cio_tx_o	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T114,T116	Yes	T5,T114,T116	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T114,T116	Yes	T5,T114,T116	OUTPUT
intr_rx_watermark_o	Yes	Yes	T5,T114,T116	Yes	T5,T114,T116	OUTPUT
intr_tx_done_o	Yes	Yes	T5,T114,T116	Yes	T5,T114,T116	OUTPUT
intr_rx_overflow_o	Yes	Yes	T5,T114,T116	Yes	T5,T114,T116	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_break_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_timeout_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T87,*T88,*T89	Yes	T87,T88,T89	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	INPUT
tl_i.a_valid	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	INPUT
tl_o.a_ready	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
tl_o.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
tl_o.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T59,*T114	Yes	T5,T59,T114	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T71,T66,T659	Yes	T71,T66,T659	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T186,T93,T94	Yes	T186,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T186,T93,T94	Yes	T186,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T71,T66,T659	Yes	T71,T66,T659	OUTPUT
cio_rx_i	Yes	Yes	T5,T45,T46	Yes	T5,T6,T17	INPUT
cio_tx_o	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T114,T272	Yes	T5,T114,T272	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T114,T272	Yes	T5,T114,T272	OUTPUT
intr_rx_watermark_o	Yes	Yes	T5,T114,T272	Yes	T5,T114,T272	OUTPUT
intr_tx_done_o	Yes	Yes	T5,T114,T272	Yes	T5,T114,T272	OUTPUT
intr_rx_overflow_o	Yes	Yes	T5,T114,T272	Yes	T5,T114,T272	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_break_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_timeout_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T116,T272,T210	Yes	T116,T272,T210	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T116,T272,T210	Yes	T116,T272,T210	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T87,*T88,*T89	Yes	T87,T88,T89	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	INPUT
tl_i.a_valid	Yes	Yes	T116,T272,T66	Yes	T116,T272,T66	INPUT
tl_o.a_ready	Yes	Yes	T116,T272,T66	Yes	T116,T272,T66	OUTPUT
tl_o.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T116,T272,T210	Yes	T116,T272,T210	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T116,T272,T210	Yes	T116,T272,T66	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T116,T272,T210	Yes	T116,T272,T66	OUTPUT
tl_o.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T116,*T272,*T210	Yes	T116,T272,T210	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T116,T272,T66	Yes	T116,T272,T66	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T658,T66,T341	Yes	T658,T66,T341	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T341,T93,T94	Yes	T93,T94,T95	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T93,T94,T95	Yes	T341,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T658,T66,T341	Yes	T658,T66,T341	OUTPUT
cio_rx_i	Yes	Yes	T116,T210,T211	Yes	T116,T23,T210	INPUT
cio_tx_o	Yes	Yes	T116,T210,T211	Yes	T116,T210,T211	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T116,T272,T210	Yes	T116,T272,T210	OUTPUT
intr_tx_empty_o	Yes	Yes	T116,T272,T210	Yes	T116,T272,T210	OUTPUT
intr_rx_watermark_o	Yes	Yes	T116,T272,T210	Yes	T116,T272,T210	OUTPUT
intr_tx_done_o	Yes	Yes	T116,T272,T210	Yes	T116,T272,T210	OUTPUT
intr_rx_overflow_o	Yes	Yes	T116,T272,T210	Yes	T116,T272,T210	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_break_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_timeout_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T87,*T88,*T89	Yes	T87,T88,T89	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	INPUT
tl_i.a_valid	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	INPUT
tl_o.a_ready	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	OUTPUT
tl_o.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	OUTPUT
tl_o.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T118,*T272,*T154	Yes	T118,T272,T154	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T273,T66,T186	Yes	T273,T66,T186	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T186,T93,T94	Yes	T186,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T186,T93,T94	Yes	T186,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T273,T66,T186	Yes	T273,T66,T186	OUTPUT
cio_rx_i	Yes	Yes	T118,T154,T291	Yes	T118,T154,T291	INPUT
cio_tx_o	Yes	Yes	T118,T154,T291	Yes	T118,T154,T291	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	OUTPUT
intr_tx_empty_o	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	OUTPUT
intr_rx_watermark_o	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	OUTPUT
intr_tx_done_o	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	OUTPUT
intr_rx_overflow_o	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_break_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_timeout_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T272,T29,T30	Yes	T272,T29,T30	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T272,T29,T30	Yes	T272,T29,T30	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T87,*T88,*T89	Yes	T87,T88,T89	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	INPUT
tl_i.a_valid	Yes	Yes	T272,T66,T29	Yes	T272,T66,T29	INPUT
tl_o.a_ready	Yes	Yes	T272,T66,T29	Yes	T272,T66,T29	OUTPUT
tl_o.d_error	Yes	Yes	T89,T91,T249	Yes	T89,T91,T249	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T272,T29,T30	Yes	T272,T29,T30	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T272,T29,T30	Yes	T272,T66,T29	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T272,T29,T30	Yes	T272,T66,T29	OUTPUT
tl_o.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T272,*T29,*T30	Yes	T272,T29,T30	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T272,T66,T29	Yes	T272,T66,T29	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T66,T186,T93	Yes	T66,T186,T93	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T186,T93,T94	Yes	T186,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T186,T93,T94	Yes	T186,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T66,T186,T93	Yes	T66,T186,T93	OUTPUT
cio_rx_i	Yes	Yes	T29,T30,T333	Yes	T29,T30,T333	INPUT
cio_tx_o	Yes	Yes	T29,T30,T333	Yes	T29,T30,T333	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T272,T29,T30	Yes	T272,T29,T30	OUTPUT
intr_tx_empty_o	Yes	Yes	T272,T29,T30	Yes	T272,T29,T30	OUTPUT
intr_rx_watermark_o	Yes	Yes	T272,T29,T30	Yes	T272,T29,T30	OUTPUT
intr_tx_done_o	Yes	Yes	T272,T29,T30	Yes	T272,T29,T30	OUTPUT
intr_rx_overflow_o	Yes	Yes	T272,T29,T30	Yes	T272,T29,T30	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_break_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_timeout_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T272,T310,T307	Yes	T272,T310,T307	OUTPUT

*Tests covering at least one bit in the range