Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.21	90.32		89.30			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T88,T91,T249	Yes	T88,T89,T91	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T88,T89,T250	Yes	T88,T89,T250	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T117,T216,T217	Yes	T117,T216,T217	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T47,T117,T216	Yes	T47,T117,T216	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T65,T88,T135	Yes	T65,T88,T135	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T65,T87,T88	Yes	T65,T87,T88	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T73,T117,T218	Yes	T73,T117,T218	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T45,T46,T47	Yes	T5,T6,T17	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T76,T78,T256	Yes	T76,T78,T256	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T45,T46,T47	Yes	T5,T6,T17	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T45,T46,T47	Yes	T5,T6,T17	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T76,T78,T256	Yes	T76,T78,T256	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T45,T46,T47	Yes	T5,T6,T17	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T76,T79,T80	Yes	T76,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T76,T78,T256	Yes	T76,T78,T256	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T80,T81,T349	Yes	T80,T81,T349	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T87,*T88,*T135	Yes	T87,T88,T135	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T77,T78,T256	Yes	T77,T78,T256	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T77,T78,T256	Yes	T77,T78,T256	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T77,T78,T256	Yes	T77,T78,T256	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T77,T78,T256	Yes	T77,T78,T256	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T77,T78,T256	Yes	T77,T78,T256	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T256	Yes	T77,T78,T256	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T77,T78,T256	Yes	T77,T78,T256	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T5,T6,T17	Yes	T45,T46,T47	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T77,T78,T256	Yes	T77,T78,T256	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T77,T78,T256	Yes	T77,T78,T256	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T45,T46,T47	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T256	Yes	T77,T78,T256	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T45,T46,T47	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T77,T78,T256	Yes	T77,T78,T256	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T6,T59,T60	Yes	T6,T59,T60	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T6,T59,T60	Yes	T6,T59,T60	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T66,T384,T385	Yes	T66,T384,T385	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T66,T384,T385	Yes	T66,T384,T385	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T66,T384,T385	Yes	T66,T384,T385	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T66,T384,T385	Yes	T66,T384,T385	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T66,T384,T385	Yes	T66,T384,T385	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T384,T385,T386	Yes	T384,T385,T386	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T87,T88,T135	Yes	T66,T67,T68	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T384,T385,T386	Yes	T66,T384,T385	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T386,*T387,*T388	Yes	T384,T385,T386	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T66,T384,T385	Yes	T66,T384,T385	INPUT
tl_peri_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_peri_i.d_error	Yes	Yes	T117,T207,T292	Yes	T117,T207,T292	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_peri_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T76,*T79,*T80	Yes	T76,T77,T78	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T26,T66,T206	Yes	T26,T66,T206	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T26,T66,T206	Yes	T26,T66,T206	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T26,T66,T206	Yes	T26,T66,T206	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T26,T66,T206	Yes	T26,T66,T206	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T26,T66,T206	Yes	T26,T66,T206	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T26,T66,T206	Yes	T26,T66,T206	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T27,T168,T170	Yes	T27,T168,T170	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T26,T66,T206	Yes	T26,T66,T206	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T26,T66,T206	Yes	T26,T66,T206	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T26,T206,T27	Yes	T26,T206,T27	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T26,T206,T27	Yes	T26,T66,T206	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T26,T206,T27	Yes	T26,T206,T27	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T26,*T206,*T27	Yes	T26,T206,T27	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T26,T66,T206	Yes	T26,T66,T206	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T66,T206,T374	Yes	T66,T206,T374	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T66,T206,T49	Yes	T66,T206,T49	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T66,T206,T374	Yes	T66,T206,T374	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T66,T206,T374	Yes	T66,T206,T374	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T66,T206,T49	Yes	T66,T206,T49	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T66,T206,T374	Yes	T66,T206,T374	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T66,T206,T374	Yes	T66,T206,T374	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T66,T206,T374	Yes	T66,T206,T374	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T206,T49,T180	Yes	T206,T49,T180	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T206,T374,T49	Yes	T66,T206,T374	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T206,T49,T180	Yes	T206,T49,T180	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T206,*T374,*T49	Yes	T206,T374,T49	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T66,T206,T374	Yes	T66,T206,T374	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T2,T272,T66	Yes	T2,T272,T66	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T2,T272,T66	Yes	T2,T272,T66	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T272,T66	Yes	T2,T272,T66	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T2,T272,T66	Yes	T2,T272,T66	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T2,T272,T66	Yes	T2,T272,T66	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T2,T272,T66	Yes	T2,T272,T66	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T2,T272,T66	Yes	T2,T272,T66	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T2,T272,T66	Yes	T2,T272,T66	INPUT
tl_usbdev_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T272,T206,T374	Yes	T272,T206,T374	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T272,T206,T374	Yes	T272,T206,T374	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T2,T272,T66	Yes	T272,T206,T31	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T2,*T272,*T66	Yes	T272,T206,T31	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T2,T272,T66	Yes	T2,T272,T66	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T45,T46,T47	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T6,T45,T59	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T80,T87,T88	Yes	T80,T87,T88	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T87,T88	Yes	T80,T87,T88	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T80,T87,T88	Yes	T80,T87,T88	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T80,T87,T88	Yes	T80,T87,T88	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T80,T87,T88	Yes	T80,T87,T88	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T80,T88,T89	Yes	T80,T88,T89	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T80,T87,T88	Yes	T80,T87,T88	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T80,T87,T88	Yes	T80,T87,T88	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T80,T87,T88	Yes	T80,T87,T88	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T80,T87,T88	Yes	T80,T87,T88	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T80,T88,T89	Yes	T80,T88,T89	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T80,*T87,*T88	Yes	T80,T87,T88	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T80,T87,T88	Yes	T80,T87,T88	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T5,T6,T18	Yes	T5,T6,T18	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T45,T46,T47	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_hmac_o.d_ready	Yes	Yes	T45,T59,T46	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T59,T104,T113	Yes	T59,T104,T113	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T59,T104,T113	Yes	T59,T104,T113	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T59,T104,T113	Yes	T59,T104,T113	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T59,T104,T113	Yes	T59,T104,T113	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T59,T104,T113	Yes	T59,T104,T113	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T104,T113,T651	Yes	T104,T113,T651	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T59,T104,T113	Yes	T59,T104,T113	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T59,T104,T113	Yes	T59,T104,T113	INPUT
tl_hmac_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T59,T104,T113	Yes	T59,T104,T113	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T104,T113	Yes	T59,T104,T113	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T59,T104,T113	Yes	T59,T104,T113	INPUT
tl_hmac_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T59,*T104,*T113	Yes	T59,T104,T113	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T59,T104,T113	Yes	T59,T104,T113	INPUT
tl_kmac_o.d_ready	Yes	Yes	T17,T97,T45	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T17,T97,T45	Yes	T17,T97,T45	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T17,T97,T45	Yes	T17,T97,T45	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T17,T97,T45	Yes	T17,T97,T45	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T17,T97,T45	Yes	T17,T97,T45	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T17,T97,T45	Yes	T17,T97,T45	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T80,*T65,*T92	Yes	T80,T65,T92	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T17,T97,T166	Yes	T17,T97,T166	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T17,T97,T45	Yes	T17,T97,T45	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T17,T97,T45	Yes	T17,T97,T45	INPUT
tl_kmac_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T17,T97,T45	Yes	T17,T97,T45	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T97,T45	Yes	T17,T97,T45	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T17,T97,T45	Yes	T17,T97,T166	INPUT
tl_kmac_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T80,*T65,*T92	Yes	T80,T65,T92	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T17,*T97,*T45	Yes	T17,T97,T166	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T17,T97,T45	Yes	T17,T97,T45	INPUT
tl_aes_o.d_ready	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T45,T126,T66	Yes	T45,T126,T66	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T45,T126,T66	Yes	T45,T126,T66	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T45,T126,T257	Yes	T45,T126,T257	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T45,T126,T66	Yes	T45,T126,T66	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T45,T126,T257	Yes	T45,T126,T257	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T45,T126,T257	Yes	T45,T126,T257	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T45,T126,T257	Yes	T45,T126,T257	INPUT
tl_aes_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T45,T126,T257	Yes	T45,T126,T257	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T126,T257	Yes	T45,T126,T257	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T45,T126,T257	Yes	T45,T126,T257	INPUT
tl_aes_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T45,*T126,*T257	Yes	T45,T126,T257	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T45,T126,T257	Yes	T45,T126,T257	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T59,T46	Yes	T5,T6,T17	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T45,T59,T46	Yes	T5,T6,T17	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T45,*T46,*T105	Yes	T45,T59,T46	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_csrng_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_csrng_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T46,T47	Yes	T5,T6,T17	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T45,T46,T47	Yes	T5,T6,T17	INPUT
tl_csrng_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T45,*T46,*T105	Yes	T45,T46,T105	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_edn0_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_edn0_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T46,T47	Yes	T5,T6,T17	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T45,T46,T47	Yes	T5,T6,T17	INPUT
tl_edn0_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T45,*T46,*T105	Yes	T45,T46,T105	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_edn1_o.d_ready	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	INPUT
tl_edn1_i.d_error	Yes	Yes	T88,T89,T250	Yes	T88,T89,T250	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	INPUT
tl_edn1_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T45,*T46,*T105	Yes	T45,T46,T105	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T45,T46,T105	Yes	T45,T46,T105	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T5,T26,T18	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T5,T26,T18	Yes	T5,T26,T18	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T26,T18	Yes	T5,T26,T18	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T5,T26,T18	Yes	T5,T26,T18	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T5,T26,T18	Yes	T5,T26,T18	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T5,T26,T18	Yes	T5,T26,T18	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T5,T26,T18	Yes	T5,T26,T18	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T5,T26,T18	Yes	T5,T26,T18	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T5,T26,T18	Yes	T5,T26,T18	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T26,T18	Yes	T5,T26,T18	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T5,T26,T18	Yes	T5,T26,T18	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T5,*T26,*T18	Yes	T5,T26,T18	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T5,T26,T18	Yes	T5,T26,T18	INPUT
tl_otbn_o.d_ready	Yes	Yes	T45,T59,T46	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T59,T105,T115	Yes	T59,T105,T115	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T59,T105,T115	Yes	T59,T105,T115	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T59,T105,T115	Yes	T59,T105,T115	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T59,T105,T115	Yes	T59,T105,T115	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T59,T105,T115	Yes	T59,T105,T115	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T90,*T65,*T171	Yes	T90,T65,T171	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T59,T105,T115	Yes	T59,T105,T115	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T59,T105,T115	Yes	T59,T105,T115	INPUT
tl_otbn_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T59,T105,T115	Yes	T59,T105,T115	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T105,T115	Yes	T59,T105,T115	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T59,T105,T115	Yes	T59,T105,T115	INPUT
tl_otbn_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T90,*T65,*T171	Yes	T90,T65,T171	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T59,*T105,*T115	Yes	T59,T105,T115	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T59,T105,T115	Yes	T59,T105,T115	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T45,T59,T46	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T45,T59,T46	Yes	T45,T59,T46	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T45,T59,T46	Yes	T45,T59,T46	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T45,T59,T46	Yes	T45,T59,T46	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T45,T59,T46	Yes	T45,T59,T46	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T45,T59,T46	Yes	T45,T59,T46	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T45,T59,T46	Yes	T45,T59,T46	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T45,T59,T46	Yes	T45,T59,T46	INPUT
tl_keymgr_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T45,T46,T108	Yes	T45,T46,T108	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T59,T46	Yes	T45,T59,T46	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T45,T59,T46	Yes	T45,T59,T46	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T45,*T59,*T46	Yes	T45,T59,T46	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T45,T59,T46	Yes	T45,T59,T46	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T19,T59,T70	Yes	T19,T59,T70	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T19,T59,T70	Yes	T19,T59,T70	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T45,T59,T46	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T78,*T88,*T89	Yes	T78,T88,T89	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T87,T88,T135	Yes	T87,T88,T135	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T201,T293,T294	Yes	T201,T293,T294	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T21,T57,T58	Yes	T59,T60,T61	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T21,T57,T58	Yes	T59,T60,T61	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T78,T88,T89	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T127,*T197,*T198	Yes	T127,T197,T198	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T45,T46,T47	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range