Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.21	90.32		89.30			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T45,T46,T47	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	INPUT
tl_main_i.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_main_o.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_main_o.d_error	Yes	Yes	T117,T207,T292	Yes	T117,T207,T292	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_main_o.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T76,*T79,*T80	Yes	T76,T77,T78	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	INPUT
tl_uart0_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	INPUT
tl_uart0_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T5,*T59,*T114	Yes	T5,T59,T114	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T5,T59,T114	Yes	T5,T59,T114	INPUT
tl_uart1_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T116,T272,T210	Yes	T116,T272,T210	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T116,T272,T210	Yes	T116,T272,T210	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T116,T272,T66	Yes	T116,T272,T66	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T116,T272,T66	Yes	T116,T272,T66	INPUT
tl_uart1_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T116,T272,T210	Yes	T116,T272,T210	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T116,T272,T210	Yes	T116,T272,T66	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T116,T272,T210	Yes	T116,T272,T66	INPUT
tl_uart1_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T116,*T272,*T210	Yes	T116,T272,T210	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T116,T272,T66	Yes	T116,T272,T66	INPUT
tl_uart2_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	INPUT
tl_uart2_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	INPUT
tl_uart2_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T118,*T272,*T154	Yes	T118,T272,T154	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T118,T272,T154	Yes	T118,T272,T154	INPUT
tl_uart3_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T272,T29,T30	Yes	T272,T29,T30	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T272,T29,T30	Yes	T272,T29,T30	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T272,T66,T29	Yes	T272,T66,T29	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T272,T66,T29	Yes	T272,T66,T29	INPUT
tl_uart3_i.d_error	Yes	Yes	T89,T91,T249	Yes	T89,T91,T249	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T272,T29,T30	Yes	T272,T29,T30	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T272,T29,T30	Yes	T272,T66,T29	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T272,T29,T30	Yes	T272,T66,T29	INPUT
tl_uart3_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T272,*T29,*T30	Yes	T272,T29,T30	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T272,T66,T29	Yes	T272,T66,T29	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T206,T209,T306	Yes	T206,T209,T306	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T206,T209,T306	Yes	T206,T209,T306	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T66,T206,T209	Yes	T66,T206,T209	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T66,T206,T209	Yes	T66,T206,T209	INPUT
tl_i2c0_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T209,T306,T80	Yes	T209,T306,T80	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T206,T209,T306	Yes	T66,T206,T209	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T206,T209,T306	Yes	T66,T206,T209	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T206,*T209,*T306	Yes	T206,T209,T306	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T66,T206,T209	Yes	T66,T206,T209	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T206,T311,T306	Yes	T206,T311,T306	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T206,T311,T306	Yes	T206,T311,T306	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T66,T206,T311	Yes	T66,T206,T311	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T66,T206,T311	Yes	T66,T206,T311	INPUT
tl_i2c1_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T311,T306,T80	Yes	T311,T306,T80	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T206,T311,T306	Yes	T66,T206,T311	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T206,T311,T306	Yes	T66,T206,T311	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T206,*T311,*T306	Yes	T206,T311,T306	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T66,T206,T311	Yes	T66,T206,T311	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T215,T206,T306	Yes	T215,T206,T306	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T215,T206,T306	Yes	T215,T206,T306	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T215,T66,T206	Yes	T215,T66,T206	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T215,T66,T206	Yes	T215,T66,T206	INPUT
tl_i2c2_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T215,T306,T80	Yes	T215,T306,T80	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T215,T206,T306	Yes	T215,T66,T206	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T215,T206,T306	Yes	T215,T66,T206	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T215,*T206,*T306	Yes	T215,T206,T306	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T215,T66,T206	Yes	T215,T66,T206	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T212,T213,T180	Yes	T212,T213,T180	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T212,T213,T180	Yes	T212,T213,T180	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T212,T66,T213	Yes	T212,T66,T213	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T212,T66,T213	Yes	T212,T66,T213	INPUT
tl_pattgen_i.d_error	Yes	Yes	T88,T89,T250	Yes	T88,T89,T250	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T212,T213,T180	Yes	T212,T213,T180	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T212,T213,T180	Yes	T212,T66,T213	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T212,T213,T180	Yes	T212,T66,T213	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T65,*T92,T88	Yes	T65,T92,T88	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T212,*T213,*T180	Yes	T212,T213,T180	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T212,T66,T213	Yes	T212,T66,T213	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T119,T214,T413	Yes	T119,T214,T413	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T119,T214,T413	Yes	T119,T214,T413	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T119,T66,T214	Yes	T119,T66,T214	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T119,T66,T214	Yes	T119,T66,T214	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T119,T214,T413	Yes	T119,T214,T413	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T119,T214,T413	Yes	T119,T66,T214	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T119,T214,T413	Yes	T119,T66,T214	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T119,*T214,*T413	Yes	T119,T214,T413	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T119,T66,T214	Yes	T119,T66,T214	INPUT
tl_gpio_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_gpio_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T306,T80,T39	Yes	T306,T80,T39	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T306,T80,T39	Yes	T1,T119,T66	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T306,T80,T39	Yes	T1,T119,T66	INPUT
tl_gpio_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T45,*T46,*T47	Yes	T5,T6,T17	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T26,T76,T206	Yes	T26,T76,T206	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T26,T76,T206	Yes	T26,T76,T206	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T26,T76,T66	Yes	T26,T76,T66	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T26,T76,T66	Yes	T26,T76,T66	INPUT
tl_spi_device_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T26,T76,T206	Yes	T26,T76,T206	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T26,T76,T206	Yes	T26,T76,T206	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T26,T76,T66	Yes	T26,T76,T206	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T26,*T76,*T66	Yes	T26,T76,T206	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T26,T76,T66	Yes	T26,T76,T66	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T119,T416,T253	Yes	T119,T416,T253	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T119,T416,T253	Yes	T119,T416,T253	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T119,T66,T416	Yes	T119,T66,T416	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T119,T66,T416	Yes	T119,T66,T416	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T416,T253,T343	Yes	T416,T253,T343	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T119,T416,T253	Yes	T119,T66,T416	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T119,T416,T253	Yes	T119,T66,T416	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T119,*T416,*T253	Yes	T119,T416,T253	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T119,T66,T416	Yes	T119,T66,T416	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T18,*T19,*T59	Yes	T18,T19,T59	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T5,T17,T26	Yes	T5,T17,T26	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T59,T46	Yes	T5,T6,T17	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T45,T59,T46	Yes	T5,T6,T17	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T97,T166	Yes	T5,T97,T166	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T5,T17,T97	Yes	T5,T17,T97	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T97,T166	Yes	T5,T97,T166	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T97,T45	Yes	T5,T6,T17	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T45,T46	Yes	T5,T6,T17	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T5,*T97,*T166	Yes	T5,T97,T166	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T65,*T92,*T88	Yes	T65,T92,T88	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T76,*T79,*T65	Yes	T76,T79,T65	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T45,*T46,*T108	Yes	T45,T46,T108	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T65,T92,T87	Yes	T65,T92,T87	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T65,T92,T87	Yes	T65,T92,T87	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T65,T92,T87	Yes	T65,T92,T87	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T5,T6,T17	Yes	T45,T46,T47	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T65,T92,T87	Yes	T65,T92,T87	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T65,T92,T87	Yes	T65,T92,T87	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T45,T46,T47	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T65,*T92,T88	Yes	T65,T92,T88	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T45,T46,T47	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T65,T92,T87	Yes	T65,T92,T87	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T59,T108,T110	Yes	T59,T108,T110	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T59,T108,T110	Yes	T59,T108,T110	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T59,T108,T110	Yes	T59,T108,T110	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T59,T108,T110	Yes	T59,T108,T110	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T59,T108,T20	Yes	T59,T108,T20	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T63,T72,T158	Yes	T63,T72,T66	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T59,T110,T20	Yes	T59,T110,T20	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T349,*T350,*T65	Yes	T349,T350,T65	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T108,*T110,*T20	Yes	T59,T108,T110	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T59,T108,T110	Yes	T59,T108,T110	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T59,T2,T60	Yes	T59,T2,T60	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T2,T60	Yes	T59,T2,T60	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T45,T59,T46	Yes	T5,T6,T17	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T45,*T59,*T46	Yes	T5,T6,T17	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T19,T59,T70	Yes	T19,T59,T70	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T19,T59,T70	Yes	T19,T59,T70	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T19,T59,T70	Yes	T19,T59,T70	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T19,T59,T70	Yes	T19,T59,T70	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T19,T59,T70	Yes	T19,T59,T70	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T59,T70	Yes	T19,T59,T70	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T19,T59,T70	Yes	T19,T59,T70	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T19,*T70,*T71	Yes	T19,T59,T70	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T19,T59,T70	Yes	T19,T59,T70	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T127,T197,T198	Yes	T127,T197,T198	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T21,T57,T58	Yes	T59,T60,T61	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T21,T57,T58	Yes	T59,T60,T61	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T127,*T197,*T198	Yes	T127,T197,T198	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T19,T45,T59	Yes	T19,T45,T59	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T45,T46,T47	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T19,T45,T59	Yes	T19,T45,T59	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T45,T59	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T19,T45,T59	Yes	T19,T45,T59	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T90,*T171,*T172	Yes	T90,T171,T172	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T18,T19,T70	Yes	T18,T19,T70	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T77,T78,T80	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T18,*T19,*T59	Yes	T18,T19,T59	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T18,T19,T59	Yes	T18,T19,T59	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T109,T2,T218	Yes	T109,T2,T218	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T109,T2,T218	Yes	T109,T2,T218	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T109,T2,T218	Yes	T109,T2,T218	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T109,T2,T218	Yes	T109,T2,T218	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T109,T2,T218	Yes	T109,T2,T218	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T218,T272	Yes	T2,T218,T272	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T109,T218,T173	Yes	T109,T2,T218	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T2,*T218,*T272	Yes	T109,T2,T218	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T109,T2,T218	Yes	T109,T2,T218	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T103,T2,T119	Yes	T103,T2,T119	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T103,T2,T119	Yes	T103,T2,T119	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T103,T2,T119	Yes	T103,T2,T119	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T103,T2,T119	Yes	T103,T2,T119	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T88,T89,T250	Yes	T88,T89,T249	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T103,T2,T120	Yes	T103,T2,T7	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T103,T2,T119	Yes	T103,T2,T119	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T103,T2,T119	Yes	T103,T2,T119	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T80,*T88,*T89	Yes	T80,T88,T89	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T103,*T2,*T119	Yes	T103,T2,T119	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T103,T2,T119	Yes	T103,T2,T119	INPUT
tl_ast_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T80,T90,T65	Yes	T80,T90,T65	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_ast_i.d_error	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T88,T135,T89	Yes	T88,T135,T89	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T46,T47	Yes	T5,T6,T17	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T45,T46,T47	Yes	T5,T6,T17	INPUT
tl_ast_i.d_sink	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T88,*T89,*T91	Yes	T88,T89,T91	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T88,T89,T91	Yes	T88,T89,T91	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T88,*T135,*T89	Yes	T88,T135,T89	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range