Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.34 99.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 99.02 99.02
tb.dut.top_earlgrey.u_edn0 99.25 99.25


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.21 90.32 89.30 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.25 99.25


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.25 99.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.21 90.32 89.30 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 75 96.15
Total Bits 1210 1202 99.34
Total Bits 0->1 605 602 99.50
Total Bits 1->0 605 600 99.17

Ports 78 75 96.15
Port Bits 1210 1202 99.34
Port Bits 0->1 605 602 99.50
Port Bits 1->0 605 600 99.17

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T5,T6,T17 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 INPUT
tl_i.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_address[6:0] Yes Yes *T87,*T88,*T89 Yes T87,T88,T89 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T80,*T88,*T89 Yes T80,T88,T89 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T87,T88,T135 Yes T87,T88,T135 INPUT
tl_i.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_o.a_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_o.d_error Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T45,T46,T47 Yes T5,T6,T17 OUTPUT
tl_o.d_data[31:0] Yes Yes T45,T46,T47 Yes T5,T6,T17 OUTPUT
tl_o.d_sink Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_source[5:0] Yes Yes *T80,*T88,*T89 Yes T80,T88,T89 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T45,*T46,*T105 Yes T45,T46,T105 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_i[0].edn_req Yes Yes T45,T46,T108 Yes T45,T46,T108 INPUT
edn_i[1].edn_req Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
edn_i[2].edn_req Yes Yes T5,T6,T17 Yes T4,T5,T6 INPUT
edn_i[3].edn_req Yes Yes T125,T402,T424 Yes T125,T402,T424 INPUT
edn_i[4].edn_req Yes Yes T5,T6,T17 Yes T4,T5,T6 INPUT
edn_i[5].edn_req Yes Yes T5,T6,T17 Yes T4,T5,T6 INPUT
edn_i[6].edn_req Yes Yes T5,T6,T17 Yes T4,T5,T6 INPUT
edn_i[7].edn_req Yes Yes T5,T6,T17 Yes T4,T5,T6 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T46,T108,T110 Yes T45,T46,T108 OUTPUT
edn_o[0].edn_fips Yes Yes T115,T257,T258 Yes T45,T46,T115 OUTPUT
edn_o[0].edn_ack Yes Yes T45,T46,T108 Yes T45,T46,T108 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[1].edn_fips No No Yes T105,T124,T179 OUTPUT
edn_o[1].edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T17,T26,T97 Yes T5,T6,T17 OUTPUT
edn_o[2].edn_fips Yes Yes T121,T122,T123 Yes T46,T124,T125 OUTPUT
edn_o[2].edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T125,T402,T424 Yes T125,T402,T424 OUTPUT
edn_o[3].edn_fips No No Yes T125,T424,T425 OUTPUT
edn_o[3].edn_ack Yes Yes T125,T402,T424 Yes T125,T402,T424 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T46,T167,T47 Yes T5,T59,T70 OUTPUT
edn_o[4].edn_fips Yes Yes T122 Yes T257,T612,T318 OUTPUT
edn_o[4].edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[5].edn_fips Yes Yes T257,T258,T612 Yes T45,T257,T125 OUTPUT
edn_o[5].edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[6].edn_fips Yes Yes T115,T257,T258 Yes T105,T115,T124 OUTPUT
edn_o[6].edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T45,T59,T47 Yes T5,T6,T26 OUTPUT
edn_o[7].edn_fips Yes Yes T115,T257,T258 Yes T115,T257,T125 OUTPUT
edn_o[7].edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T45,T46,T47 Yes T5,T6,T17 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
csrng_cmd_i.genbits_fips Yes Yes T115,T371,T611 Yes T45,T46,T105 INPUT
csrng_cmd_i.genbits_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T257,T258,T612 Yes T257,T258,T612 INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T66,T186,T93 Yes T66,T186,T93 INPUT
alert_rx_i[0].ping_n Yes Yes T186,T93,T94 Yes T186,T93,T94 INPUT
alert_rx_i[0].ping_p Yes Yes T186,T93,T94 Yes T186,T93,T94 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T613,T66,T614 Yes T613,T66,T614 INPUT
alert_rx_i[1].ping_n Yes Yes T186,T93,T94 Yes T186,T93,T94 INPUT
alert_rx_i[1].ping_p Yes Yes T186,T93,T94 Yes T186,T93,T94 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T66,T186,T93 Yes T66,T186,T93 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T613,T66,T614 Yes T613,T66,T614 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T133,T306,T308 Yes T133,T306,T308 OUTPUT
intr_edn_fatal_err_o Yes Yes T306,T308,T309 Yes T306,T308,T309 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 48 96.00
Total Bits 714 707 99.02
Total Bits 0->1 357 354 99.16
Total Bits 1->0 357 353 98.88

Ports 50 48 96.00
Port Bits 714 707 99.02
Port Bits 0->1 357 354 99.16
Port Bits 1->0 357 353 98.88

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 INPUT
tl_i.a_mask[3:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 INPUT
tl_i.a_address[6:0] Yes Yes *T87,*T88,*T89 Yes T87,T88,T89 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T45,T46,T105 Yes T45,T46,T105 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T45,*T46,*T105 Yes T45,T46,T105 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T45,*T46,*T105 Yes T45,T46,T105 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T80,*T88,*T89 Yes T80,T88,T89 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T87,T88,T135 Yes T87,T88,T135 INPUT
tl_i.a_valid Yes Yes T45,T46,T105 Yes T45,T46,T105 INPUT
tl_o.a_ready Yes Yes T45,T46,T105 Yes T45,T46,T105 OUTPUT
tl_o.d_error Yes Yes T88,T89,T250 Yes T88,T89,T250 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 OUTPUT
tl_o.d_data[31:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 OUTPUT
tl_o.d_sink Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_source[5:0] Yes Yes *T80,*T88,*T89 Yes T80,T88,T89 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T45,*T46,*T105 Yes T45,T46,T105 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T45,T46,T105 Yes T45,T46,T105 OUTPUT
edn_i[0].edn_req Yes Yes T115,T124,T257 Yes T115,T124,T257 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T115,T124,T257 Yes T115,T124,T257 OUTPUT
edn_o[0].edn_fips Yes Yes T115,T257,T258 Yes T115,T124,T257 OUTPUT
edn_o[0].edn_ack Yes Yes T115,T124,T257 Yes T115,T124,T257 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T45,T46,T105 Yes T45,T46,T105 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T115,T124,T257 Yes T45,T46,T105 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T45,T46,T105 Yes T45,T46,T105 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T45,T115,T124 Yes T115,T124,T257 INPUT
csrng_cmd_i.genbits_fips No No Yes T115,T371,T611 INPUT
csrng_cmd_i.genbits_valid Yes Yes T45,T46,T105 Yes T45,T46,T105 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T45,T46,T105 Yes T45,T46,T105 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T257,T258,T612 Yes T257,T258,T612 INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T66,T186,T93 Yes T66,T186,T93 INPUT
alert_rx_i[0].ping_n Yes Yes T186,T93,T94 Yes T186,T93,T94 INPUT
alert_rx_i[0].ping_p Yes Yes T186,T93,T94 Yes T186,T93,T94 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T613,T66,T93 Yes T613,T66,T93 INPUT
alert_rx_i[1].ping_n Yes Yes T93,T94,T95 Yes T93,T94,T96 INPUT
alert_rx_i[1].ping_p Yes Yes T93,T94,T96 Yes T93,T94,T95 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T66,T186,T93 Yes T66,T186,T93 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T613,T66,T93 Yes T613,T66,T93 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T133,T306,T308 Yes T133,T306,T308 OUTPUT
intr_edn_fatal_err_o Yes Yes T306,T308,T309 Yes T306,T308,T309 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 74 94.87
Total Bits 1208 1199 99.25
Total Bits 0->1 604 601 99.50
Total Bits 1->0 604 598 99.01

Ports 78 74 94.87
Port Bits 1208 1199 99.25
Port Bits 0->1 604 601 99.50
Port Bits 1->0 604 598 99.01

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T45,T46,T47 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T5,T6,T17 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 INPUT
tl_i.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_address[6:0] Yes Yes *T87,*T88,*T89 Yes T87,T88,T89 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T80,*T88,*T89 Yes T80,T88,T89 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T87,T88,T135 Yes T87,T88,T135 INPUT
tl_i.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_o.a_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_o.d_error Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T45,T46,T105 Yes T45,T46,T105 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T45,T46,T47 Yes T5,T6,T17 OUTPUT
tl_o.d_data[31:0] Yes Yes T45,T46,T47 Yes T5,T6,T17 OUTPUT
tl_o.d_sink Yes Yes T88,T89,T91 Yes T88,T89,T91 OUTPUT
tl_o.d_source[5:0] Yes Yes *T80,*T88,*T89 Yes T80,T88,T89 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T45,*T46,*T105 Yes T45,T46,T105 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_i[0].edn_req Yes Yes T45,T46,T108 Yes T45,T46,T108 INPUT
edn_i[1].edn_req Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
edn_i[2].edn_req Yes Yes T5,T6,T17 Yes T4,T5,T6 INPUT
edn_i[3].edn_req Yes Yes T125,T402,T424 Yes T125,T402,T424 INPUT
edn_i[4].edn_req Yes Yes T5,T6,T17 Yes T4,T5,T6 INPUT
edn_i[5].edn_req Yes Yes T5,T6,T17 Yes T4,T5,T6 INPUT
edn_i[6].edn_req Yes Yes T5,T6,T17 Yes T4,T5,T6 INPUT
edn_i[7].edn_req Yes Yes T5,T6,T17 Yes T4,T5,T6 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T46,T108,T110 Yes T45,T46,T108 OUTPUT
edn_o[0].edn_fips No No Yes T45,T46,T219 OUTPUT
edn_o[0].edn_ack Yes Yes T45,T46,T108 Yes T45,T46,T108 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[1].edn_fips No No Yes T105,T124,T179 OUTPUT
edn_o[1].edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T17,T26,T97 Yes T5,T6,T17 OUTPUT
edn_o[2].edn_fips Yes Yes T121,T122,T123 Yes T46,T124,T125 OUTPUT
edn_o[2].edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T125,T402,T424 Yes T125,T402,T424 OUTPUT
edn_o[3].edn_fips No No Yes T125,T424,T425 OUTPUT
edn_o[3].edn_ack Yes Yes T125,T402,T424 Yes T125,T402,T424 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T46,T167,T47 Yes T5,T59,T70 OUTPUT
edn_o[4].edn_fips Yes Yes T122 Yes T257,T612,T318 OUTPUT
edn_o[4].edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[5].edn_fips Yes Yes T257,T258,T612 Yes T45,T257,T125 OUTPUT
edn_o[5].edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[6].edn_fips Yes Yes T115,T257,T258 Yes T105,T115,T124 OUTPUT
edn_o[6].edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T45,T59,T47 Yes T5,T6,T26 OUTPUT
edn_o[7].edn_fips Yes Yes T115,T257,T258 Yes T115,T257,T125 OUTPUT
edn_o[7].edn_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T45,T46,T47 Yes T5,T6,T17 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
csrng_cmd_i.genbits_fips Yes Yes T115,T371,T611 Yes T45,T46,T105 INPUT
csrng_cmd_i.genbits_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T257,T258,T612 Yes T257,T258,T612 INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T66,T93,T80 Yes T66,T93,T80 INPUT
alert_rx_i[0].ping_n Yes Yes T93,T94,T95 Yes T93,T95,T241 INPUT
alert_rx_i[0].ping_p Yes Yes T93,T95,T241 Yes T93,T94,T95 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T66,T614,T615 Yes T66,T614,T615 INPUT
alert_rx_i[1].ping_n Yes Yes T186,T93,T94 Yes T186,T93,T94 INPUT
alert_rx_i[1].ping_p Yes Yes T186,T93,T94 Yes T186,T93,T94 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T66,T93,T80 Yes T66,T93,T80 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T66,T614,T615 Yes T66,T614,T615 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T133,T306,T308 Yes T133,T306,T308 OUTPUT
intr_edn_fatal_err_o Yes Yes T306,T308,T309 Yes T306,T308,T309 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%