LINE 18005
EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T5,T6,T115 |
| 1 | 0 | 1 | Covered | T100,T405,T103 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T100,T255,T256 |
LINE 18008
EXPRESSION (addr_hit[201] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T5,T6,T115 |
| 1 | 0 | 1 | Covered | T103 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T112,T113,T114 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |